ispLEVER Classic 2.0.00.17.20.15 Fitter Report File
Copyright(C), 1992-2012, Lattice Semiconductor Corporation
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Project_Summary
Project Name : tlc_engine_v1b
Project Path : C:\ispLEVER_Classic2_0\examples\tlc_engine_v1b
Project Fitted on : Tue Nov 28 21:14:12 2017
Device : M4256_96
Package : 144
GLB Input Mux Size : 33
Available Blocks : 16
Speed : -5
Part Number : LC4256V-5T144C
Source Format : Schematic_VHDL
Project 'tlc_engine_v1b' Fit Successfully!
Compilation_Times
Prefit Time 0 secs
Load Design Time 0.01 secs
Partition Time 0.02 secs
Place Time 0.00 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
Total Input Pins 2
Total Logic Functions 21
Total Output Pins 8
Total Bidir I/O Pins 0
Total Buried Nodes 13
Total Flip-Flops 18
Total D Flip-Flops 7
Total T Flip-Flops 11
Total Latches 0
Total Product Terms 102
Total Reserved Pins 0
Total Locked Pins 10
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 2
Total Unique Resets 1
Total Unique Presets 1
Fmax Logic Levels 2
Device_Resource_Summary
Device
Total Used Not Used Utilization
-----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 1 3 --> 25
Input-Only Pins 10 0 10 --> 0
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 94 9 85 --> 9
Logic Functions 256 21 235 --> 8
Input Registers 96 0 96 --> 0
GLB Inputs 576 77 499 --> 13
Logical Product Terms 1280 65 1215 --> 5
Occupied GLBs 16 5 11 --> 31
Macrocells 256 21 235 --> 8
Control Product Terms:
GLB Clock/Clock Enables 16 1 15 --> 6
GLB Reset/Presets 16 0 16 --> 0
Macrocell Clocks 256 0 256 --> 0
Macrocell Clock Enables 256 1 255 --> 0
Macrocell Enables 256 0 256 --> 0
Macrocell Resets 256 0 256 --> 0
Macrocell Presets 256 0 256 --> 0
Global Routing Pool 356 20 336 --> 5
GRP from IFB .. 2 .. --> ..
(from input signals) .. 2 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 18 .. --> ..
----------------------------------------------------------------------
<Note> 1 : The available PT is the product term that has not been used.
<Note> 2 : IFB is I/O feedback.
<Note> 3 : MFB is macrocell feedback.
GLB_Resource_Summary
# of PT
--- Fanin --- I/O Input Macrocells Macrocells Logic clusters
Unique Shared Total Pins Regs Used Inaccessible available PTs used
-------------------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
-------------------------------------------------------------------------------------------
GLB A 0 12 12 0/6 0 4 0 12 15 4
GLB B 0 0 0 0/6 0 0 0 16 0 0
GLB C 0 0 0 0/6 0 0 0 16 0 0
GLB D 0 12 12 0/6 0 3 0 13 15 4
-------------------------------------------------------------------------------------------
GLB E 0 0 0 0/6 0 0 0 16 0 0
GLB F 6 11 17 0/6 0 2 0 14 7 2
GLB G 1 15 16 5/6 0 7 0 9 15 8
GLB H 8 12 20 4/6 0 5 0 11 13 6
-------------------------------------------------------------------------------------------
GLB I 0 0 0 0/6 0 0 0 16 0 0
GLB J 0 0 0 0/6 0 0 0 16 0 0
GLB K 0 0 0 0/6 0 0 0 16 0 0
GLB L 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
GLB M 0 0 0 0/6 0 0 0 16 0 0
GLB N 0 0 0 0/6 0 0 0 16 0 0
GLB O 0 0 0 0/6 0 0 0 16 0 0
GLB P 0 0 0 0/6 0 0 0 16 0 0
-------------------------------------------------------------------------------------------
TOTALS: 15 62 77 9/96 0 21 0 235 65 24
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 0 0
GLB C 0 0 0 0 0 0 0
GLB D 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB E 0 0 0 0 0 0 0
GLB F 0 0 0 0 0 0 0
GLB G 0 0 0 0 0 0 0
GLB H 1 0 0 1 0 0 0
------------------------------------------------------------------------------
GLB I 0 0 0 0 0 0 0
GLB J 0 0 0 0 0 0 0
GLB K 0 0 0 0 0 0 0
GLB L 0 0 0 0 0 0 0
------------------------------------------------------------------------------
GLB M 0 0 0 0 0 0 0
GLB N 0 0 0 0 0 0 0
GLB O 0 0 0 0 0 0 0
GLB P 0 0 0 0 0 0 0
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_HOLD (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
| Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
-------------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 |VCCIO0 | - | | | | |
4 | I_O | 0 |C12 | | | |
5 | I_O | 0 |C10 | | | |
6 | I_O | 0 |C8 | | | |
7 | I_O | 0 |C6 | | | |
8 | I_O | 0 |C4 | | | |
9 | I_O | 0 |C2 | | | |
10 |GNDIO0 | - | | | | |
11 | I_O | 0 |D14 | | | |
12 | I_O | 0 |D12 | | | |
13 | I_O | 0 |D10 | | | |
14 | I_O | 0 |D8 | | | |
15 | I_O | 0 |D6 | | | |
16 | I_O | 0 |D4 | | | |
17 | IN0 | 0 | | | | |
18 | NC | - | | | | |
19 |VCCIO0 | - | | | | |
20 | IN1 | 0 | | | | |
21 | I_O | 0 |E2 | | | |
22 | I_O | 0 |E4 | | | |
23 | I_O | 0 |E6 | | | |
24 | I_O | 0 |E8 | | | |
25 | I_O | 0 |E10 | | | |
26 | I_O | 0 |E12 | | | |
27 |GNDIO0 | - | | | | |
28 | I_O | 0 |F2 | | | |
29 | I_O | 0 |F4 | | | |
30 | I_O | 0 |F6 | | | |
31 | I_O | 0 |F8 | | | |
32 | I_O | 0 |F10 | | | |
33 | I_O | 0 |F12 | | | |
34 |VCCIO0 | - | | | | |
35 | TCK | - | | | | |
36 | VCC | - | | | | |
37 | GND | - | | | | |
38 | IN2 | 0 | | | | |
39 | I_O | 0 |G12 | | | |
40 | I_O | 0 |G10 | * |PCI | Output|ADDR_A
41 | I_O | 0 |G8 | * |PCI | Output|ADDR_B
42 | I_O | 0 |G6 | * |PCI | Output|ADDR_C
43 | I_O | 0 |G4 | * |PCI | Output|ADDR_D
44 | I_O | 0 |G2 | * |PCI | Output|ADDR_E
45 | IN3 | 0 | | | | |
46 |GNDIO0 | - | | | | |
47 |VCCIO0 | - | | | | |
48 | I_O | 0 |H12 | | | |
49 | I_O | 0 |H10 | * |PCI | Output|EOF_OUT
50 | I_O | 0 |H8 | * |PCI | Output|GSCLK_OUT
51 | I_O | 0 |H6 | * |PCI | Output|ADDRCLK_OUT
52 | I_O | 0 |H4 | * |LVCMOS33_5V | Input |run
53 | I_O | 0 |H2 | | | |
54 |INCLK1 | 0 | | * |LVCMOS33_5V | Input |clk
55 |GNDIO1 | - | | | | |
56 |INCLK2 | 1 | | | | |
57 | VCC | - | | | | |
58 | I_O | 1 |I2 | | | |
59 | I_O | 1 |I4 | | | |
60 | I_O | 1 |I6 | | | |
61 | I_O | 1 |I8 | | | |
62 | I_O | 1 |I10 | | | |
63 | I_O | 1 |I12 | | | |
64 |VCCIO1 | - | | | | |
65 |GNDIO1 | - | | | | |
66 | I_O | 1 |J2 | | | |
67 | I_O | 1 |J4 | | | |
68 | I_O | 1 |J6 | | | |
69 | I_O | 1 |J8 | | | |
70 | I_O | 1 |J10 | | | |
71 | I_O | 1 |J12 | | | |
72 | IN4 | 0 | | | | |
73 | GND | - | | | | |
74 | TMS | - | | | | |
75 |VCCIO1 | - | | | | |
76 | I_O | 1 |K12 | | | |
77 | I_O | 1 |K10 | | | |
78 | I_O | 1 |K8 | | | |
79 | I_O | 1 |K6 | | | |
80 | I_O | 1 |K4 | | | |
81 | I_O | 1 |K2 | | | |
82 |GNDIO1 | - | | | | |
83 | I_O | 1 |L14 | | | |
84 | I_O | 1 |L12 | | | |
85 | I_O | 1 |L10 | | | |
86 | I_O | 1 |L8 | | | |
87 | I_O | 1 |L6 | | | |
88 | I_O | 1 |L4 | | | |
89 | IN5 | 1 | | | | |
90 | NC | - | | | | |
91 |VCCIO1 | - | | | | |
92 | IN6 | 1 | | | | |
93 | I_O | 1 |M2 | | | |
94 | I_O | 1 |M4 | | | |
95 | I_O | 1 |M6 | | | |
96 | I_O | 1 |M8 | | | |
97 | I_O | 1 |M10 | | | |
98 | I_O | 1 |M12 | | | |
99 |GNDIO1 | - | | | | |
100 | I_O | 1 |N2 | | | |
101 | I_O | 1 |N4 | | | |
102 | I_O | 1 |N6 | | | |
103 | I_O | 1 |N8 | | | |
104 | I_O | 1 |N10 | | | |
105 | I_O | 1 |N12 | | | |
106 |VCCIO1 | - | | | | |
107 | TDO | - | | | | |
108 | VCC | - | | | | |
109 | GND | - | | | | |
110 | IN7 | 1 | | | | |
111 | I_O | 1 |O12 | | | |
112 | I_O | 1 |O10 | | | |
113 | I_O | 1 |O8 | | | |
114 | I_O | 1 |O6 | | | |
115 | I_O | 1 |O4 | | | |
116 | I_O | 1 |O2 | | | |
117 | IN8 | 1 | | | | |
118 |GNDIO1 | - | | | | |
119 |VCCIO1 | - | | | | |
120 | I_O | 1 |P12 | | | |
121 | I_O | 1 |P10 | | | |
122 | I_O | 1 |P8 | | | |
123 | I_O | 1 |P6 | | | |
124 | I_O | 1 |P4 | | | |
125 | I_O/OE| 1 |P2 | | | |
126 |INCLK3 | 1 | | | | |
127 |GNDIO0 | - | | | | |
128 |INCLK0 | 0 | | | | |
129 | VCC | - | | | | |
130 | I_O/OE| 0 |A2 | | | |
131 | I_O | 0 |A4 | | | |
132 | I_O | 0 |A6 | | | |
133 | I_O | 0 |A8 | | | |
134 | I_O | 0 |A10 | | | |
135 | I_O | 0 |A12 | | | |
136 |VCCIO0 | - | | | | |
137 |GNDIO0 | - | | | | |
138 | I_O | 0 |B2 | | | |
139 | I_O | 0 |B4 | | | |
140 | I_O | 0 |B6 | | | |
141 | I_O | 0 |B8 | | | |
142 | I_O | 0 |B10 | | | |
143 | I_O | 0 |B12 | | | |
144 | IN9 | 0 | | | | |
-------------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
Input_Signal_List
Input
Pin Fanout
Pin GLB Type Pullup Signal
-------------------------------------------------
54 -- INCLK 1 -------H-------- Hold clk
52 H I/O 5 A--D-FGH-------- Hold run
-------------------------------------------------
Output_Signal_List
I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
------------------------------------------------------------------------------------
51 H 3 1 2 1 DFF * S * ---------------- Fast Hold ADDRCLK_OUT
40 G 11 1 1 1 TFF * R 3 -----FGH-------- Fast Hold ADDR_A
41 G 12 1 1 1 TFF * R 3 -----FGH-------- Fast Hold ADDR_B
42 G 13 1 1 1 TFF * R 3 -----FGH-------- Fast Hold ADDR_C
43 G 14 1 1 1 TFF * R 3 -----FGH-------- Fast Hold ADDR_D
44 G 15 1 1 1 TFF * R 2 -----F-H-------- Fast Hold ADDR_E
49 H 8 1 1 1 DFF * R * ---------------- Fast Hold EOF_OUT
50 H 2 1 1 1 COM ---------------- Fast Hold GSCLK_OUT
------------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Bidir_Signal_List
I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
Buried_Signal_List
I C P R P Node
N L Mc R E U C I F Fanout
Mc GLB P LL PTs S Type E S P E R P Signal
-------------------------------------------------------------------------
12 G 11 - 2 1 COM 1 -------H-------- ADDRCLK_OUT_0
1 A 12 1 4 1 DFF * R 5 A--D-FGH-------- C0_j_0_
3 F 12 1 5 1 DFF * R 5 A--D-FGH-------- C0_j_1_
3 A 12 1 4 1 TFF * R 5 A--D-FGH-------- C0_j_2_
5 D 12 1 4 1 TFF * R 5 A--D-FGH-------- C0_j_3_
1 G 12 1 8 2 DFF * R 5 A--D-FGH-------- C0_j_4_
2 D 12 1 8 2 DFF * R 5 A--D-FGH-------- C0_j_5_
3 H 12 1 7 2 DFF * R 5 A--D-FGH-------- C0_j_6_
6 A 12 1 4 1 TFF * R 5 A--D-FGH-------- C0_j_7_
5 H 12 1 2 1 TFF * S 5 A--D-FGH-------- C0_j_8_
10 A 12 1 3 1 TFF * R 5 A--D-FGH-------- C0_next_state_0_
10 D 12 1 3 1 TFF * R 5 A--D-FGH-------- C0_next_state_1_
9 F 16 - 2 1 COM 1 -------H-------- EOF_OUT_0
-------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = ORP bypass used
PostFit_Equations
ADDRCLK_OUT.D = !C0_next_state_0_.Q ; (1 pterm, 1 signal)
ADDRCLK_OUT.C = !clk ; (1 pterm, 1 signal)
ADDRCLK_OUT.CE = ADDRCLK_OUT_0 ; (1 pterm, 1 signal)
ADDRCLK_OUT.AP = !run ; (1 pterm, 1 signal)
ADDRCLK_OUT_0 = !C0_next_state_0_.Q & !C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q ; (2 pterms, 11 signals)
ADDR_A.T = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& C0_next_state_0_.Q ; (1 pterm, 10 signals)
ADDR_A.C = !clk ; (1 pterm, 1 signal)
ADDR_A.AR = !run ; (1 pterm, 1 signal)
ADDR_B.T = ADDR_A.Q & !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q
& !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& C0_next_state_0_.Q ; (1 pterm, 11 signals)
ADDR_B.C = !clk ; (1 pterm, 1 signal)
ADDR_B.AR = !run ; (1 pterm, 1 signal)
ADDR_C.T = ADDR_B.Q & ADDR_A.Q & !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q
& !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q
& !C0_j_8_.Q & C0_next_state_0_.Q ; (1 pterm, 12 signals)
ADDR_C.C = !clk ; (1 pterm, 1 signal)
ADDR_C.AR = !run ; (1 pterm, 1 signal)
ADDR_D.T = ADDR_C.Q & ADDR_B.Q & ADDR_A.Q & !C0_j_0_.Q & !C0_j_1_.Q
& !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q
& !C0_j_7_.Q & !C0_j_8_.Q & C0_next_state_0_.Q ; (1 pterm, 13 signals)
ADDR_D.C = !clk ; (1 pterm, 1 signal)
ADDR_D.AR = !run ; (1 pterm, 1 signal)
ADDR_E.T = ADDR_D.Q & ADDR_C.Q & ADDR_B.Q & ADDR_A.Q & !C0_j_0_.Q & !C0_j_1_.Q
& !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q
& !C0_j_7_.Q & !C0_j_8_.Q & C0_next_state_0_.Q ; (1 pterm, 14 signals)
ADDR_E.C = !clk ; (1 pterm, 1 signal)
ADDR_E.AR = !run ; (1 pterm, 1 signal)
C0_j_0_.D = !( !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q
& !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_next_state_0_.Q & !C0_next_state_1_.Q
# C0_j_0_.Q & C0_next_state_0_.Q
# C0_j_0_.Q & C0_next_state_1_.Q ) ; (4 pterms, 11 signals)
C0_j_0_.C = !clk ; (1 pterm, 1 signal)
C0_j_0_.AR = !run ; (1 pterm, 1 signal)
C0_j_1_.D = !( !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q
& !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & C0_j_1_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & C0_j_1_.Q & C0_next_state_1_.Q
# !C0_j_1_.Q & !C0_next_state_0_.Q & !C0_next_state_1_.Q
# C0_j_0_.Q & !C0_j_1_.Q ) ; (5 pterms, 11 signals)
C0_j_1_.C = !clk ; (1 pterm, 1 signal)
C0_j_1_.AR = !run ; (1 pterm, 1 signal)
C0_j_2_.T = !( !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q
& !C0_j_7_.Q & !C0_j_8_.Q
# !C0_next_state_0_.Q & !C0_next_state_1_.Q
# C0_j_1_.Q
# C0_j_0_.Q ) ; (4 pterms, 11 signals)
C0_j_2_.C = !clk ; (1 pterm, 1 signal)
C0_j_2_.AR = !run ; (1 pterm, 1 signal)
C0_j_3_.T.X1 = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q ; (3 pterms, 11 signals)
C0_j_3_.T.X2 = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q ; (1 pterm, 9 signals)
C0_j_3_.C = !clk ; (1 pterm, 1 signal)
C0_j_3_.AR = !run ; (1 pterm, 1 signal)
C0_j_4_.D = !( !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & C0_j_4_.Q
& C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & C0_j_4_.Q
& C0_next_state_1_.Q
# !C0_j_4_.Q & !C0_next_state_0_.Q & !C0_next_state_1_.Q
# C0_j_3_.Q & !C0_j_4_.Q
# C0_j_2_.Q & !C0_j_4_.Q
# C0_j_1_.Q & !C0_j_4_.Q
# C0_j_0_.Q & !C0_j_4_.Q ) ; (8 pterms, 11 signals)
C0_j_4_.C = !clk ; (1 pterm, 1 signal)
C0_j_4_.AR = !run ; (1 pterm, 1 signal)
C0_j_5_.D.X1 = C0_j_0_.Q
# C0_j_1_.Q
# C0_j_2_.Q
# C0_j_3_.Q
# C0_j_4_.Q
# !C0_next_state_0_.Q & !C0_next_state_1_.Q
# !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q ; (7 pterms, 11 signals)
C0_j_5_.D.X2 = !C0_j_5_.Q ; (1 pterm, 1 signal)
C0_j_5_.C = !clk ; (1 pterm, 1 signal)
C0_j_5_.AR = !run ; (1 pterm, 1 signal)
C0_j_6_.D.X1 = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_6_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_6_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_7_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_7_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_8_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & C0_j_8_.Q & C0_next_state_1_.Q ; (6 pterms, 11 signals)
C0_j_6_.D.X2 = C0_j_6_.Q ; (1 pterm, 1 signal)
C0_j_6_.C = !clk ; (1 pterm, 1 signal)
C0_j_6_.AR = !run ; (1 pterm, 1 signal)
C0_j_7_.T = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & C0_j_8_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & C0_j_7_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & C0_j_8_.Q & C0_next_state_1_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & C0_j_7_.Q & C0_next_state_1_.Q ; (4 pterms, 11 signals)
C0_j_7_.C = !clk ; (1 pterm, 1 signal)
C0_j_7_.AR = !run ; (1 pterm, 1 signal)
C0_j_8_.T = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & C0_j_8_.Q & C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_next_state_0_.Q
& C0_next_state_1_.Q ; (2 pterms, 11 signals)
C0_j_8_.C = !clk ; (1 pterm, 1 signal)
C0_j_8_.AP = !run ; (1 pterm, 1 signal)
C0_next_state_0_.T = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q
& !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& !C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& !C0_next_state_1_.Q
# !C0_next_state_0_.Q & !C0_next_state_1_.Q ; (3 pterms, 11 signals)
C0_next_state_0_.C = !clk ; (1 pterm, 1 signal)
C0_next_state_0_.AR = !run ; (1 pterm, 1 signal)
C0_next_state_1_.T = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q
& !C0_j_4_.Q & !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& C0_next_state_0_.Q
# !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& C0_next_state_1_.Q
# C0_next_state_0_.Q & C0_next_state_1_.Q ; (3 pterms, 11 signals)
C0_next_state_1_.C = !clk ; (1 pterm, 1 signal)
C0_next_state_1_.AR = !run ; (1 pterm, 1 signal)
EOF_OUT.D = ADDR_E.Q & ADDR_D.Q & ADDR_C.Q & ADDR_B.Q & ADDR_A.Q
& C0_next_state_0_.Q ; (1 pterm, 6 signals)
EOF_OUT.C = !clk ; (1 pterm, 1 signal)
EOF_OUT.CE = EOF_OUT_0 ; (1 pterm, 1 signal)
EOF_OUT.AR = !run ; (1 pterm, 1 signal)
EOF_OUT_0 = !C0_j_0_.Q & !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q
& !C0_j_5_.Q & !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q
& C0_next_state_1_.Q
# ADDR_E.Q & ADDR_D.Q & ADDR_C.Q & ADDR_B.Q & ADDR_A.Q & !C0_j_0_.Q
& !C0_j_1_.Q & !C0_j_2_.Q & !C0_j_3_.Q & !C0_j_4_.Q & !C0_j_5_.Q
& !C0_j_6_.Q & !C0_j_7_.Q & !C0_j_8_.Q & C0_next_state_0_.Q ; (2 pterms, 16 signals)
GSCLK_OUT = clk & C0_next_state_0_.Q ; (1 pterm, 2 signals)