Hi Kokoon, thank you for the patches - there are really nice ones! :) But to a more important topic: ARGH!!! I also noticed this with your patches, and to say it short: it's not a software, but a design bug! Fortunately it can be easily fixed. To make it short: the SID is clocked asynchronously to the PIC. Depending on the clock phase between the SID and the PIC, a setup or hold violation can happen at the chip select line if the bus access is done at the "wrong moment" (rising edge on b