Does MIOS32_IIC support Core slave transfers?

[Duggle]

I should mention that I'm using STM32 Core.

 

I've found a good code example in the STM32F10x peripheral library 3.3 where the demo sets up I2C1 and I2C2 as master and slave respectively then initiates a read and a write between the ports. This example seems not to be included with the latest peripheral library. I discovered it by googling and it exists in GIThub under a project called "Thinner Client" for anyone interested.

 

It appears that there is almost no difference (if any?) in initialisation calls between master and slave mode. So my question is:

Does MIOS32_IIC support slave mode on the core side?

 

The example code above seems straight forward enough to adapt but it would be nice to use the MIOS32 library wherever possible.

[Duggle]

Update:

I have implemented the demo master/slave self test mentioned above in a MIOS32 app.

The call to the test routine is made from the App init. It returns a successful result (I can see it working with the source level debugger in Eclipse) but shortly after that (before it can print the result to MIOS Studio terminal) it crashes. 

 

I guess this underlines the benefit of using only MIOS32 library routines (where possible).

 

The test routine alters settings in the NVIC (nested vector interrupt controller) which might be the source of the problem. I'm using the MIOS32_DONT_USE_IIC switch. 

 

I can post code or code snippets if that would help.

The code I'm using is from here

[Duggle]

Just a gentle bump.

I haven't spent more time with this, but I'm confident of getting it to work.

TK, is there any prospect of adding core slave IIC transfers to MIOS32?