Hi George,  You want to wire SO (serial output) from the Core to SI (serial input) on the AOUT_NG. The top row of J19 is:   Vs Vd SO SC RC1 0V, 5V, serial out, serial clock, chip select 1.   J1 on AOUT_NG is:   Vs Vd CS SI SC 0V, 5V, chip select, serial input, serial clock.   You can see how the chip select jumps into the middle and pushes SI and SC over. So wiring up an IDC like I showed is one way around this mismatch. You could still use this cable with the line driver board ignoring the JAOU