jkeyzer

Thorsten, Thanks! That clears it up. Jeff

Hi there, I have a technical question about the approach to timing for data transfers in the midibox SID. I have noticed that on the SID daughter boards that the SID gets its own 1.0MHz oscillator, which is connected only to the phase2 clock input of the SID (and nothing else). Given that this clock is not synchronous to the PIC's clock on the host board, how does the PIC ensure that data is latched correctly by the SID? I thought that the SID latched data on the falling edge of the phase2 clock? If the clocks are unconnected, how does the PIC know when the data will be latched, to avoid latching it twice or corrupting the data etc? I am trying to better understand the SID interface and am in the process of gathering the parts to build one of these very interesting and unique synthesizers! Thanks for any info! Jeff