Bus capacity and cable length of I2C Bus

[Screaming_Rabbit]

Does anybody have experience how long the I2C bus lines can be without running into trouble?

In other words: Without calculating the capcity... what is the average cable lenght while still being on the safe side?

Thanks and greets

Roger

[stryd_one]

This is not an answer really, but I expect that the practical max length will vary greatly depending in cable used...

[Screaming_Rabbit]

THX stryd. - Your answer gave me some imput for googling (... and I finally found some time to do so).

I was surfing a bit... for your interest (I put the links to the wiki too):

• Original-Specifikation NXP Semiconductors V2.1 http://www.nxp.com/acrobat/literature/9398/39340011.pdf
  
• Original-Specifikation NXP Semiconductors V03 http://www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf
  

From: http://www.esacademy.com/faq/i2c/q_and_a/i2cqena.htm

Question: What is the maximum distance of the I2C bus?

This depends on the load of the bus and the speed you run at. In typical applications, the length is a few meters (9-12ft). The maximum capacitive load has been specified (see also the electrical Spec's in the I2C FAQ). Another thing to be taken into account is the amount of noise picked up by long cabling. This noise can disturb the signal transmitted over the bus so badly that it becomes unreadable.

The length can be increased significantly by running at a lower clock frequency. One particular application - clocked at about 500Hz - had a bus length of about 100m (300ft). If you are careful in routing your PCB's and use proper cabling (twisted pair and/or shielded cable), you can also gain some length.

If you need to go far at high speed, you can use an active current source instead of a simple pull-up resistor. Philips has a standalone product for this purpose. Using a charge pump also reduces "ghost signals" caused by reflections at the end of the bus lines.

From the Spec:

17.3 Wiring pattern of the bus lines

In general, the wiring must be so chosen that crosstalk and

interference to/from the bus lines is minimized. The bus

lines are most susceptible to crosstalk and interference at

the HIGH level because of the relatively high impedance of

the pull-up devices.

If the length of the bus lines on a PCB or ribbon cable

exceeds 10 cm and includes the VDD and VSS lines, the

wiring pattern must be:

--SDA

--VDD

--VSS

--SCL

If only the VSS line is included, the wiring pattern must be:

--SDA

--VSS

--SCL

These wiring patterns also result in identical capacitive

loads for the SDA and SCL lines. The VSS and VDD lines

can be omitted if a PCB with a VSS and/or VDD layer is

used.

If the bus lines are twisted-pairs, each bus line must be

twisted with a VSS return. Alternatively, the SCL line can be

twisted with a VSS return, and the SDA line twisted with a

VDD return. In the latter case, capacitors must be used to

decouple the VDD line to the VSS line at both ends of the

twisted pairs.

If the bus lines are shielded (shield connected to VSS),

interference will be minimized. However, the shielded

cable must have low capacitive coupling between the SDA

and SCL lines to minimize crosstalk.

Greets, Roger

[stryd_one]

Thanks Rog'!