AOUT + AIN + EURO

[latigid on]

I loaded up ain_jitter_mon to check the performance of AIN_4:

 

Test conditions are a 5V reference into the input (normalisation), attenuation of this to min/mid/max using the on board pot (this pot doesn't go all the way to 0V/ground to protect the TL072 op amp output). AIN4-7 are jumpered to ground at the Core.

Each point is a 1 second sample with the difference between maximum and minimum value plotted. ADC resolution is full 12-bit, so even with a jitter of 20 it's ~0.5% error. I think that'll probably be acceptable with CV inputs that are changing over time. Apparently there's also the possibility of oversampling.

For reference, the figures look pretty similar to simply connecting a pot to 0V/3v3, so my guess is that the STM chip is the main culprit for noisy ADCs :).