error compiling c app

[audiocommander]

symbol not previously defined "bit"..

that's what we were laughing about: a bit is either 0 or 1 it cannot be -1 (or maybe stryd_one is sitting in front of one of these mysterious quantum computers cooled down to -250°C with an ice beard developing the seq Vx to conquer the world) ;D

just take an unsigned char – that's the smallest possible variable type besides some custom typedefs...

you have to take care, that no variable name is used in the c-namespace that hasn't been defined or declared... maybe it helps to peek in a basic c book, there are some excellent free online-books. you should have read the pure basics (variables, scopes, syntax) in one day... it's not very difficult, esp. when you consider that SDCC just knows the plain basics of this language – so don't let it scare you by a thousand pages, it's mostly only the first 50 relevant for PIC dev ;)

cheers ;)

Michael

[moxi]

maybe it helps to peek in a basic c book, there are some excellent free online-books. you should have read the pure basics (variables, scopes, syntax) in one day... it's not very difficult, esp. when you consider that SDCC just knows the plain basics of this language – so don't let it scare you by a thousand pages, it's mostly only the first 50 relevant for PIC dev

...i'm now reading the page 3 of my C book ;), i think i will spend some day to read it more  and more...

in fact i can't stand to loose fighting against a machine! my little brain will learn where to put all this "{" and "}"... >:(

[TK.]

Moxi, I don't understand why you are not using the original code of aout.c and doing the changes there?

AOUT_Load2SR() has to transfer 16 bits instead of 32, it has to service the RCLK pin instead of the CS pin (compare with aout_lc driver)

AOUT_Update() has to select the values which should be uploaded to the shift registers...

and thats all!

Best Regards, Thorsten.

Best Regards, Thorsten.

[moxi]

hi,

AOUT_Load2SR() has to transfer 16 bits instead of 32

that mean i  only need "aout_sr0" now...sorry if i'm totally off

[TK.]

Did you try it?

Best Regards, Thorsten.

[moxi]

Did you try it?

the compilation work removing it...

i've to understand how to swap the pin before hardware test...

[stryd_one]

Yeh totally, I was so busy trying to get the MBCV aout_lc driver working, I never thought of that! Then again, I have never really looked at the aout modules before, and didn't realise how they worked....

At least we all just learned heaps about using ASM in the C wrapper :D

How's this sound:

add defines for the rclk pin:

#define CV_AOUT_LC_LAT_RCLK LATC ; The latch enable input

#define CV_AOUT_LC_TRIS_RCLK TRISC ; is connected to Port C.5

#define CV_AOUT_LC_PIN_RCLK 5 ; (CANNOT be shared with other outputs!)

then change:

movlw 32 ; init loop counter

to

movlw 16 ; init loop counter

so it only does 16 bits

replace

bsf AOUT_LAT_CS, AOUT_PIN_CS; deactivate chip select

with

bsf CV_AOUT_LC_LAT_RCLK, CV_AOUT_LC_PIN_RCLK; RClock low

(and also do that change in the Init function where the pin is cleared)

Am I on the right track there?

[moxi]

then change:

  movlw  32            ; init loop counter

to

  movlw  16            ; init loop counter

yes, i've done this ...

but if you replace just the define "##define AOUT_LAT_CS    _LATC"

by "#define CV_AOUT_LC_LAT_RCLK  LATC ", i suppose you don't make any change in the hardware pin configuration , you're just renaming a define....

the Aout_LC is not connected the same way than the Aout module....

there is a "little complication", i've spend the night on...i go on now with the head more fresh...

[stryd_one]

feel free to drop me an email :)

[moxi]

I'm lost...

it has to service the RCLK pin instead of the CS pin (compare with aout_lc driver)

for me: define of LC driver

#define CV_AOUT_LC_LAT_RCLK LATC ; The latch enable input

#define CV_AOUT_LC_TRIS_RCLK TRISC ; is connected to Port C.5

#define CV_AOUT_LC_PIN_RCLK 5 ; (CANNOT be shared with other outputs!)

;

#define CV_AOUT_LC_LAT_DOUT LATC ; The data pin

#define CV_AOUT_LC_TRIS_DOUT TRISC ; is connected to Port C.4

#define CV_AOUT_LC_PIN_DOUT 4 ; (can be shared with other outputs)

;

#define CV_AOUT_LC_LAT_SCLK LATD ; The shift clock input pin SCLK

#define CV_AOUT_LC_TRIS_SCLK TRISD ; is connected to Port D.5

#define CV_AOUT_LC_PIN_SCLK 5 ; (can be shared with other outputs)

do exactly the same thing than:

// common AOUT connections (MIDIbox CV pinning)

#define AOUT_LAT_CS _LATC // The chip select pin CS#

#define AOUT_TRIS_CS _TRISC // is connected to Port C.5

#define AOUT_PIN_CS 5 // (CANNOT be shared with other outputs!)

//

#define AOUT_LAT_DIN _LATC // The data input pin DIN

#define AOUT_TRIS_DIN _TRISC // is connected to Port C.4

#define AOUT_PIN_DIN 4 // (can be shared with other outputs)

//

#define AOUT_LAT_SCLK _LATD // The shift clock input pin SCLK

#define AOUT_TRIS_SCLK _TRISD // is connected to Port D.5

#define AOUT_PIN_SCLK 5 // (can be shared with other outputs)

i mean that for me this two defines define the same pins...(but i know that the connection are different for the two module...i'm missing something...probably i didn't sleep enough...

how it's done the difference for addressing different pin?

[stryd_one]

Nah they're not quite the same...

#define CV_AOUT_LC_LAT_RCLK   LATC   ; The latch enable input

Means that when you refer to the RCLK pin in code as "CV_AOUT_LC_LAT_RCLK", the precompiler will replace that with "LATC", Which is the latch register for port C on the PIC

#define CV_AOUT_LC_TRIS_RCLK   TRISC   ; is connected to Port C.5

Same kind of thing, this refers to TRISC which is the tristate register for the port (makes it an In or Output) For example this code clears the register which enables the pins as outputs:

CV_AOUT_LC_Init
	;; enable pin drivers
	bcf	CV_AOUT_LC_TRIS_RCLK, CV_AOUT_LC_PIN_RCLK
	bcf	CV_AOUT_LC_TRIS_DOUT, CV_AOUT_LC_PIN_DOUT
	bcf	CV_AOUT_LC_TRIS_SCLK, CV_AOUT_LC_PIN_SCLK

And this one replaces the pin designation with a number:

#define CV_AOUT_LC_PIN_RCLK   5   ; (CANNOT be shared with other outputs!) 

So basically all those defines are to use PORTC pin 5 as an output.... So:

// common AOUT connections (MIDIbox CV pinning)
#define AOUT_LAT_CS      _LATC   // The chip select pin CS#
#define AOUT_TRIS_CS      _TRISC   // is connected to Port C.5
#define AOUT_PIN_CS      5   // (CANNOT be shared with other outputs!)
//
#define AOUT_LAT_DIN      _LATC   // The data input pin DIN
#define AOUT_TRIS_DIN      _TRISC   // is connected to Port C.4
#define AOUT_PIN_DIN      4   // (can be shared with other outputs)
//
#define AOUT_LAT_SCLK      _LATD   // The shift clock input pin SCLK
#define AOUT_TRIS_SCLK      _TRISD   // is connected to Port D.5
#define AOUT_PIN_SCLK      5   // (can be shared with other outputs)

Means CS = C5 DIN = C4 SCLK = D5 and

#define CV_AOUT_LC_LAT_RCLK   LATC   ; The latch enable input
#define CV_AOUT_LC_TRIS_RCLK   TRISC   ; is connected to Port C.5
#define CV_AOUT_LC_PIN_RCLK   5   ; (CANNOT be shared with other outputs!)
;
#define CV_AOUT_LC_LAT_DOUT   LATC   ; The data pin
#define CV_AOUT_LC_TRIS_DOUT   TRISC   ; is connected to Port C.4
#define CV_AOUT_LC_PIN_DOUT   4   ; (can be shared with other outputs)
;
#define CV_AOUT_LC_LAT_SCLK   LATD   ; The shift clock input pin SCLK
#define CV_AOUT_LC_TRIS_SCLK   TRISD   ; is connected to Port D.5
#define CV_AOUT_LC_PIN_SCLK   5   ; (can be shared with other outputs)

RCLK = C5

DOUT = C4

SCLK = D5

:)

[stryd_one]

yes, i've done this ...

but if you replace just the define "##define AOUT_LAT_CS     _LATC"

by "#define CV_AOUT_LC_LAT_RCLK   LATC ", i suppose you don't make any change in the hardware pin configuration , you're just renaming a define....

Not sure how, but I missed this post. Yeh you're right, it pretty much is just renaming the define...

from the ucapps page:

Following projects support the MBHP_AOUT_LC module - note that the pinning to the Core module is different:

Schematic AOUT_LC:J1:SO AOUT_LC:J1:SC AOUT_LC:J1:RC

MIDIbox CV CORE:J10:RC (RC4) CORE:J10:MD (RD5) CORE:J10:SO (RC5)

MIDIbox SID (*) CORE:J6:SC (RC1) CORE:J6:RC (RC0) CORE:J6:SI (RC3)

As you can see, the pins you use can vary... Just pick whichever ones suit you best, I guess :)

[moxi]

Means

CS = C5    << pin RC5?

DIN = C4    << pin RC4?

SCLK = D5  << pin RD5?

....

means

RCLK = C5    << pin RC5?

DOUT = C4    << pin RC4?

SCLK = D5    << pin RD5?

...the connections are different for the two modules...so, again, where is done the difference...maybe i'm it's alzheimer disease that is comin on my mind...

"je tourne en rond"

[stryd_one]

Yeh well so long as the wires are soldered to the correct pin, it seems the same  ???

Ahh I see what TK means, it's the driving of the pins... Hang 5....

[stryd_one]

How's this:

void AOUT_Load2SR(unsigned int sr0_value, unsigned int sr1_value)
{
  aout_sr0 = sr0_value;
  aout_sr1 = sr1_value;

__asm
        bcf     AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; clear clock	COPIED FROM MBCV DRIVER
	;; bcf	AOUT_LAT_CS, AOUT_PIN_CS	; activate chip select	NOT NEEDED FOR AOUT_LC

	;; I believe that the below might be able to be ignored for the AOUT_LC?
	;; you will notice that the instructions are sometimes arranged
	;; in a special order to ensure proper output signals - for example:
	;; between a rising and a falling SCLK edge there is at least one
	;; other instruction to ensure that the high pulse of the SCLK
	;; is longer than 100 nS (the MAX525 datasheet specifies at least 40 nS)

	banksel _loop_ctr
	movlw	16				; init loop counter	ONLY 16 BIT FOR _LC
	movwf	_loop_ctr, BANKED

	;; This is the same as the original AOUT driver with the names changed, and the latching copied from the MBCV
AOUT_Load2SR_Loop:
	banksel _aout_sr0
	bcf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT	; set DOUT depending on current MSB
	btfsc	_aout_sr1+1, 7, BANKED
	bsf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT
	rlcf	_aout_sr0+0, F, BANKED		; start to shift the 16-bit value
	rlcf	_aout_sr0+1, F, BANKED		; second step for the 16-bit shift
	bsf	AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; rising clock edge
	rlcf	_aout_sr1+0, F, BANKED		; third step for the 16-bit shift
	rlcf	_aout_sr1+1, F, BANKED		; last step for the 16-bit shift
	bcf	AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; falling clock edge

	banksel _loop_ctr
	decfsz	_loop_ctr, F, BANKED		; loop 16 times	ONLY 16 BIT FOR _LC
	bra	AOUT_Load2SR_Loop

	;; bsf	AOUT_LAT_CS, AOUT_PIN_CS; deactivate chip select	NOT NEEDED FOR AOUT_LC

	bsf     AOUT_LC_LAT_RCLK, AOUT_LC_PIN_RCLK	; latch SID values	COPIED FROM MBCV DRIVER
	bcf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT	; clear out pin (standby)	COPIED FROM MBCV DRIVER
	bcf     AOUT_LC_LAT_RCLK, AOUT_LC_PIN_RCLK	; release latch	COPIED FROM MBCV DRIVER

__endasm;
}

It's basically the original AOUT driver from the toolbox, but with the new names for the pins, and the clocking/latching stolen from the MBCV AOUT_LC driver. You'll notice the difference is that the CS line is not clocked like it is in the original (at the beginning and end of the code, look for "NOT NEEDED FOR AOUT_LC"), but the RCLK line is.... I think that's what TK means ;)

[moxi]

It's one of prog i've tested...but that not pass the hardware test..

[stryd_one]

I wasn't so sure about the clocking either... try this:

void AOUT_Load2SR(unsigned int sr0_value, unsigned int sr1_value)
{
  aout_sr0 = sr0_value;
  aout_sr1 = sr1_value;

__asm
        bcf     AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; clear clock	COPIED FROM MBCV DRIVER
	;; bcf	AOUT_LAT_CS, AOUT_PIN_CS	; activate chip select	NOT NEEDED FOR AOUT_LC

	;; I believe that the below might be able to be ignored for the AOUT_LC?
	;; you will notice that the instructions are sometimes arranged
	;; in a special order to ensure proper output signals - for example:
	;; between a rising and a falling SCLK edge there is at least one
	;; other instruction to ensure that the high pulse of the SCLK
	;; is longer than 100 nS (the MAX525 datasheet specifies at least 40 nS)

	banksel _loop_ctr
	movlw	16				; init loop counter	ONLY 16 BIT FOR _LC
	movwf	_loop_ctr, BANKED

	;; This is the same as the original AOUT driver with the names changed, and the latching copied from the MBCV
AOUT_Load2SR_Loop:
	banksel _aout_sr0
	bcf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT	; set DOUT depending on current MSB
	btfsc	_aout_sr1+1, 7, BANKED
	bsf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT
	rlcf	_aout_sr0+0, F, BANKED		; start to shift the 16-bit value
	rlcf	_aout_sr0+1, F, BANKED		; second step for the 16-bit shift

	rlcf	_aout_sr1+0, F, BANKED		; third step for the 16-bit shift
	rlcf	_aout_sr1+1, F, BANKED		; last step for the 16-bit shift

	bsf	AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; rising clock edge	MOVED FOR AOUT_LC DRIVER
	bcf	AOUT_LC_LAT_SCLK, AOUT_LC_PIN_SCLK	; falling clock edge

	banksel _loop_ctr
	decfsz	_loop_ctr, F, BANKED		; loop 16 times	ONLY 16 BIT FOR _LC
	bra	AOUT_Load2SR_Loop

	;; bsf	AOUT_LAT_CS, AOUT_PIN_CS; deactivate chip select	NOT NEEDED FOR AOUT_LC

	bsf     AOUT_LC_LAT_RCLK, AOUT_LC_PIN_RCLK	; latch SID values	COPIED FROM MBCV DRIVER
	bcf	AOUT_LC_LAT_DOUT, AOUT_LC_PIN_DOUT	; clear out pin (standby)	COPIED FROM MBCV DRIVER
	bcf     AOUT_LC_LAT_RCLK, AOUT_LC_PIN_RCLK	; release latch	COPIED FROM MBCV DRIVER

__endasm;
}

Of course you can rename the variables just make sure they're all the same... And just make sure the AOUT_LC lines are connected to the correct pins :)

Oh yeh, are you using one _LC or two?

[moxi]

i've tried to change the hardware pinning...no success

in fact , i need more explanation about

it has to service the RCLK pin instead of the CS pin (compare with aout_lc driver)

when i compare the defines in aout.h and the ones at the beginning of the LC driver, i see the same thing but with two different names...changing the name of the defines (eg replacing

"#define AOUT_LAT_CS"

by

"#define CV_AOUT_LC_LAT_RCLK"

and doing the same replacement in the prog won't lead to any changes...the app is still adressing the same pins...and if i'm right , i've to adress different pins to adress the LC module...

as i don't understand how pin are serviced, it don't mean a thing of trying many combination of prog'..

it's what i'm doing since 3 day's...and even if i make it work, i won't understand why..

Oh yeh, are you using one _LC or two?

i'm using two LC module, but just making the first one working would be enough in a first time...

[stryd_one]

in fact , i need more explanation about

when i compare the defines in aout.h and the ones at the beginning of the LC driver, i see the same thing but with two different names...changing the name of the defines (eg replacing

"#define AOUT_LAT_CS"

by

"#define CV_AOUT_LC_LAT_RCLK"

and doing the same replacement in the prog won't lead to any changes...the app is still adressing the same pins...and if i'm right , i've to adress different pins to adress the LC module...

Well lets look at what they do:

AOUT from Toolbox:

SCLK Low

CS Low

: Load the bits loop

DIN Low

DIN High (if the bit is set)

Shift bits

SCLK High

Shift bits again to keep SCLK high for long enough to keep the MAX525 happy

SCLK Low

:Do the loop until they're all loaded

CS High

Now AOUT_LC from MBCV:

SCLK Low

: Load the bits loop

DOUT Low

DOUT High (if the bit is set)

SCLK High

SCLK Low

Shift bits

:Do the loop until they're all loaded

RCLK High

DOUT Low

RCLK Low

....I'm pretty sure that's what my last code does? But I'm not sure the bits are being shifted off correctly :\

[moxi]

it's ok for the understanding of the asm code...

but to say that in other words:

1.how to define that there is the RCLK pin that is used instead of the CS pin?

are changes to be done in the aout.h file?

2.why defines of pins are the same in the two drivers (in midibox CV app) and hardware pining is different?

==> i'm missing something...

[TK.]

As Stryd_one mentioned, the purpose of the "Register Clock" is different than the purpose of a "Chip Select" line. At the end it doesn't much matter, to which pins these signals are assigned, you just only have to take care, that a chip select line is active during the whole transfer (AOUT module), and a register clock is triggered after a transfer (AOUT_LC module)

You could even call the "RCLK" pin still "CS" pin - the name is not important (it could only confuse others if they read the code)

Stryd_One's code is correct, but you have to take care, that only the 16 bits of sr1_value are shifted out

Why different defines? Because for different MIDIbox variation, where pins are sometimes allocated by other functions...

Best Regards, Thorsten.

[moxi]

ok,

but what about my question:

2.why defines of pins are the same in the two drivers (in midibox CV app) and hardware pining is different?

==> i'm missing something...

you wrote two time the same code for defining pins (in aout_lc and aout driver of mbCV app) but at this end the modules are connected to diferent pins..how it's possible?

[TK.]

I don't understand this question - why shouldn't it be possible?

Best Regards, Thorsten.

[moxi]

in the aout_lc driver, there is this code:

; AOUT_LC driver

;

#if 1

;; common AOUT_LC connections

#define CV_AOUT_LC_LAT_RCLK LATC ; The latch enable input

#define CV_AOUT_LC_TRIS_RCLK TRISC ; is connected to Port C.5

#define CV_AOUT_LC_PIN_RCLK 5 ; (CANNOT be shared with other outputs!)

;

#define CV_AOUT_LC_LAT_DOUT LATC ; The data pin

#define CV_AOUT_LC_TRIS_DOUT TRISC ; is connected to Port C.4

#define CV_AOUT_LC_PIN_DOUT 4 ; (can be shared with other outputs)

;

#define CV_AOUT_LC_LAT_SCLK LATD ; The shift clock input pin SCLK

#define CV_AOUT_LC_TRIS_SCLK TRISD ; is connected to Port D.5

#define CV_AOUT_LC_PIN_SCLK 5 ; (can be shared with other outputs)

#endif

and in the aout driver :

; The pins to which the first CV_AOUT module is connected have to be defined here:

;

#if 1

;; common AOUT connections

#define CV_AOUT_LAT_CS LATC ; The chip select pin CS#

#define CV_AOUT_TRIS_CS TRISC ; is connected to Port C.5

#define CV_AOUT_PIN_CS 5 ; (CANNOT be shared with other outputs!)

;

#define CV_AOUT_LAT_DIN LATC ; The data input pin DIN

#define CV_AOUT_TRIS_DIN TRISC ; is connected to Port C.4

#define CV_AOUT_PIN_DIN 4 ; (can be shared with other outputs)

;

#define CV_AOUT_LAT_SCLK LATD ; The shift clock input pin SCLK

#define CV_AOUT_TRIS_SCLK TRISD ; is connected to Port D.5

#define CV_AOUT_PIN_SCLK 5 ; (can be shared with other outputs)

#else

for me,reading this code, that are the same pins that are defined for the two modules (c5,c4 and d5), but in fact the module are NOT connected to the same pins..

so i suppose there is something i'm understanding wrong..

[TK.]

I still don't get it...

You are selecting one of the drivers (they don't run in parallel)

The clock line is always connected to pin RD5

The data line is always connected to pin RC4

The CS/RCLK line is always connected to pin RC5

in these two configurations. Of course, you can connect the modules to other pins if they are free or if they are allowed to be shared, in this case you only need to change the constant values of the #define's

Best Regards, Thorsten.