TL

@TK: Thx, I've searched already something like this but found nothing... ;D @all: My current opinion towards the module: 2 latches for addresses ( or maybe even 3 latches, this way 128k x 8, 256k x 8, 512k x 8 and even bigger SRAM sizes could be used ) 3-to-8 decoder to drive the latch enables, etc. battery backup the same board layout for different SRAM sizes (e.g. 128k x 8, 256k x 8 and 512k x 8 ) design the board as piggy-back for the core module Comments ? ;D

What's the actual state of this module? ;D

Yes, I think this would be great. ;D Right. Hopefully my spare time (IT business is sometimes really a spare time killer :P ) and missing parts will allow me to test it this week... ;D Thank you for your encouraging words... Actually I'm totally new to Eagle... ::) and yes I've learned the last 2 days a lot! ;D In theory this would be possible, II don't know actually if different sized of SRAMs are pincompatible in some way... A few thoughts about using 2 latches ore only one latch: Wouldn't it simplify the calculation of the address lines if 2 latches are used which are connected to RB of the PIC? Just take the low byte of the address and put in latch 1, take the high byte put it in latch 2, put the remaining A16 line to one pin of J5, and read/write to/from the SRAM. Or is putting A8-A15 in the second latch eating more time than the software calculation and spreading the high byte to the 3 different ports RA, RE and RC of the core ? Actually I'm relative new to PIC asm ( I've done a few things ace ages ago with 8051 derivates) and don't know about this point... :P Any statements? Maybe Stryd_one or TK ? ;)

Great, d2k's board is much nicer than mine ;D Well, I guess I've to learn a lot... :) Please keep in mind the schematic is not tested at the moment. I'm going to build one on perfboard and test it this week. Unfortunately I've to build a core module first ( all my core's are in my SID ) and wait for the PIC from Voti and the SRAM from Reichelt. @d2k: Would you mind to send me the changed schematic / board file ? I would then do the documentation (create nice pdf's of the schematic and board, connection diagram) of this module after verifying the circuit works.

Here is my first pcb design. This is my very first pcb design, so I don't know if it would work in the real world... Any comments about this are welcome... :)

And here is the schematic of Thorsten's idea: Download Please keep in mind that both designs are a little bit simlified since the bypass caps are missing, which are important for the SRAM... And I'm not sure about the use of J7 / SC, maybe another pin of the core should be used instead... Thorsten ? ;)

Did you search this ? http://www.digit-life.com/articles/livetolive51/

at least one latch is needed, because the core has not enough pins free to use for the address lines... I think I will do the schematic Torsten suggested tomorrow... Why address and data separated? with the address lines a cell within the sram is selected and with the data lines the content of this cell is read or written. Here is a short description who different ram types work: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html I hope my description and the link will help you... :)

I've done a quick schematic Download It's not tested so I don't know if it works... ;)

http://www.hynix.com/datasheet/pdf/sram/HY628100B(Rev12).pdf Cross reference list: Hynix HY628100B Samsung K6F1008R2A Cypress CY62128V18 NEC PD441000L-DX Toshiba TC551001C Hitachi HM628128D

Wouldn't it be easier (and maybe even faster) to use D0-D7 from the LCD for both the address and the data lines of the SRAM using 2 Latches for the address lines? Since it simplyfies the connection of the SRAM module to the core (only 8 Connections from RB0-RB7) and some pins of J5 for ALE of latches, the remaining address lines (A17), R/W, etc. And it would simplify the calculation of the address bits to output: take the low byte (D0-D7)of the SRAM address put it in the first latch, put the high byte (D8-D15) of the address to the second latch, set some pin of J5 to the value of A16 and read/write the data to/from the SRAM. If this would make sense, I could make a schematic the next few days...

new Version with random patches creation for SID & FM ;D Download: http://www.automatic-brain.de/midibox/

The chips arrived here today, too... Thank you very much ! ;D

Great work, Thorsten! ;D And just in time the new MidiBox Patch Manager 0.7 with support for MidiBox SID and FM is available, too. :)

@DrBunsen: Well, if I find the time to do the port from Delphi to FreePascal there will be a Linux and a MacOS X, too. Unfortunately, my time is very limited at the moment by it's on my todo list... :) @all New version 0.7 out with support for the MidiBox FM ! Download: http://www.automatic-brain.de/midibox

maybe you want a MIDI Thru, too? And you need only one Sub-D, since Banksticks are only connected to the first (master) PIC.

jau: Anonsten genauso wie auf in der Beschreibung vom JDM auf ucapps.de. Und natürlich _MUSS_ der Treiber vom JDM für W2K installiert sein...

Ich denke daß es an den RS-232 Chips der Rechner liegt. Unter http://ucapps.de/mbhp_jdm.html ganz unten ist beschrieben wie man ein Netzteil oder 2 9V Batterien anschließt um zu den 13.7V zu kommen.., Ich habe hier einen neueren Athlon Rechner bei dem ich dasselbe tun musste, bei meinem alten Dual P3 brauche ich ich kein externes Netzteil...

Some comments about the 0.5 release?

*update* Version 0. 5 available Download Changes: -full support of multiple banksticks ( backup and restore all banks with one click) - Patch Manager now gets a bank via the <Request a Dump of the whole Bank> SysEx command

Und du hast keine Probleme damit ? ;D

I've just setup a small webpage for the Patch Manager: http://www.automatic-brain.de/midibox/ Currently I'm working on support for backing up all banksticks with one click...

Jetzt gibts ne neue Version die SID 1.7 unterstützt... ;)

Ok, new version 0.4 available: Download Changes: - support for MB SID 1.7 firmware (supports multiple banksticks) - more than one selected patch can saved to SysEx file - bugfix in log, now every midi event is logged TK reported that the Patch Manager sometimes chrashed with WinXP and his MidiSport 2x2 :( Please test the new release and report your results...