game console, generating the screen display, sound effects, and reading input controller.
Clock and CPU Synchronization:
The 3.58 MHz oscillator (OSC Pin) also clocks a divide by three counter on this chip whose output (1.19 Mhz) is buffered to drive an output pin called 00.
This pin provides the input phase zero clock to the microprocessor which then produces the system 02 clock (1.19 Mhz).
Thus, the final input clock is 02, you've just got to bypass CPU, pin 00 connected to pin 02 and reproduce the OSC stage.
There's two types of OSC one for the NTSC (3,58Mhz) and another for PAL/Secam (3,54MHz) according to your country video norm.
The frequency of clock running has a direct bearing on the sound generator. In PAL, sounds will drop a little in pitch (frequency) because of a slower crystal clock.
Two independent audio generating circuits are included, each with programmable frequency, noise content, and volume control registers.
2 voices, named AUD0 and AUD1.
With a TIA in NTSC version, each voice has its output (pin 12 & 13).
In PAL version, the two voices are added to the same output (pin 13), pin 12 is used for carrier frequency modulation.
So rather choose a NTSC version if you want 2 separate outputs.
Each audio circuit consists of parts described below:
Clock pulses (at approximately 30 KHz) from the horizontal sync counter pass through a divide by N circuit which is controlled by the output code from a five bit frequency register (AUDF).
This register can be loaded (written) by the microprocessor at any time, and causes the 30 KHz clocks to be divided by 1 (code 00000) through 32 (code 11111).
This produces pulses that are digitally adjustable from approximately 30 KHz to 1 KHz and are used to clock the noise-tone generator.
This circuit contains a nine bit shift counter which may be controlled by the output code from a four bit audio control register(AUDC), and is clocked by the frequency select circuit.
The control register can be loaded by the microprocessor at any time, and selects different shift counter feedback taps and count lengths to produce a variety of noise and tone qualities.
The shift counter output is used to drive the audio output pad through four driver transistors that are graduated in size.
Each transistor is twice as large as the previous one and is enable by one bit from the audio volume register (AUDV).
This audio volume register may be loaded by the microprocessor at any time. As binary codes 0 through 15 are loaded, the pad drive transistors are enabled in a binary sequence.
The shift counter output therefore can pull down on the audio output pad with 16 selectable impedance levels.
There are 44 8-bit registers whose addresses are coded on 6 bits.
AUDx registers adresses start @ 0x15
So we need 4 bits of address only. And 5 bits max for data (frequency).
Data bits 7,6,5 and Adress bit 6 are connected to ground. Adress bit 5 to 5v.
Frequency registers AUDFx:
This registers are limited to 32 valuesâ€‹â€‹ (5 bits), and need to be reversed!
Control registers AUDCx:
These are 16 in number (4 bits). But some are the same or are silent.
So only 10 waveforms are available.
Volume registers AUDVx:
16 levels (4 bits).
Schematic for MBHP Platform, Thorsten style:
Next part: MB-TIA Cartridge. Max Manager Software and Drum Kit Sound Demo.