Jump to content

Configuring 8 gates/clocks/triggers with line extender


Altitude
 Share

Recommended Posts

Could use some help here since I have not done it before.  I have my 4xDOUT board and assume I have to edit the config file to get the gates/clocks/triggers up and running.  This is what I have added:

 

I have my Gate 1 wired to D0 on the board so everything needs to be backwards (I assume)

 

 

 


##################################################
# CV and Gate/Trigger/Sync Setup
##################################################

# AOUT interface now selected in CV Configuration Menu and stored in MBSEQ_GC.V4 file
# please scroll through the menu to find this page!

# the 8 CV gates can be assigned to a shift register (0=off, 1-32: number of shift register):
# - 1st CV Gate available at DOUT SR output D7
# - 2nd CV Gate available at DOUT SR output D6
# - 3rd CV Gate available at DOUT SR output D5
# - ...
# - 8th CV Gate available at DOUT SR output D0
CV_GATE_SR1   8    
CV_GATE_SR2   7
CV_GATE_SR3   6
CV_GATE_SR4   5
CV_GATE_SR5   4
CV_GATE_SR6   3
CV_GATE_SR7   2
CV_GATE_SR8   1

# and DIN Clock Outputs can be assigned to a shift register as well (0=off, 1-32: number of shift register):
# D7..D0 will output individual clock or start/stop signals which can be configured in the CV configuration page
CLK_SR1        16
CLK_SR2        15
CLK_SR3        14
CLK_SR4        13
CLK_SR5        12
CLK_SR6        10
CLK_SR7        9

# additional gate triggers are available on common digital output pins of the
# DOUT shift register chain - they are assigned to AOUT channel #16 (Note C-1, C#1, D-1, ...)
# define the shift registers which should be used here (each provides 8 gates)
# Note that SRs assigned to this function cannot be used as LED outputs (exclusive function)
# Allowed values: 1-32, 0 disables the function, all other values invalid and not allowed
DOUT_GATE_SR1   24
DOUT_GATE_SR2   23
DOUT_GATE_SR3   22
DOUT_GATE_SR4   21
DOUT_GATE_SR5   20
DOUT_GATE_SR6   19
DOUT_GATE_SR7   18
DOUT_GATE_SR8   17

# if set to 1, the DOUT "gates" will send 1mS pulses
# useful for analog drums
DOUT_1MS_TRIGGER 1

# should J5A/B/C outputs be enabled (0: no, 1: yes, 2: yes, but in open drain mode)?
#  - the 6 first AOUT gates will be forwarded to J5A/B
#  - the remaining last 2 AOUT gates are available at J5C.A10 and J5C.A11 (LPC17: J28.WS and J28.MCLK)
#  - DIN sync clock will be forwarded to J5C:A0 (LPC17: J28.SDA)
#  - DIN sync start/stop will be forwarded to J5C:A1 (LPC17: J28.SC)
#  - if open drain mode enabled (option 2), external pull-ups have to be connected to J5 pins
#    (advantage: pin levels can be pulled to 5V)
#
# NEVER USE THIS TOGETHER WITH ANALOG POTS - IT WILL CAUSE A SHORT CIRCUIT!
J5_ENABLED 1

Link to comment
Share on other sites

I think you're misinterpreting the config file, I still have an F1 Core so I haven't done this myself yet, but as far as I can see you assign a whole shift register ("SR") to a set of 8 gates, triggers or clocks. The additional DOUT_GATE_SR* are for 64 extra trigger outs not associated with the usual 8 AOUT channels.

So try

CV_GATE_SR1   n

where n = your desired SR. Then build a custom ribbon cable with the last 8 strands twisted 180 degrees into one of the IDCs. This should correct the mirroring.

Link to comment
Share on other sites

>I think you're misinterpreting the config file

That goes without question :)  This is uncharted inferiority for me, I'm not very cody..

That makes more sense.  So the SRs at the end of the Dout chain (past the CS,into the line extender, then out to the 595s) are sequential per 8 outputs (i.e. the first 595 is "1" the second is "2" and so forth?)

Will a mirrored cable work for me? everything is hardwired on the PCB.

How about the J5 line, should that be off?

 

AOUTEUROJACK.png

 

 

Edited by Altitude
Link to comment
Share on other sites

Success!  Thanks Andy!

For anyone else:

The additional gate/clocks/triggers are SR 3,4,5 respectively on the SEQV4 with WIlba's control surface.

I am backwards on my wiring however, what I thought was gate/clk/trigger 1 is in fact 8, can this be remedied by messing with the cable or do I need to redo the board?

Edited by Altitude
Link to comment
Share on other sites

Great that it works (as you figured out, you need to account for any SRs previously assigned to the CS, TPD etc.).

 

Just now, Altitude said:

I am backwards on my wiring however, what I thought was gate/clk/trigger 1 is in fact 8, can this be remedied by messing with the cable or do I need to redo the board?

It should be okay to flip the last 8 strands around as I mentioned before? Not Vss/Vdd of course...

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Loading...
 Share

×
×
  • Create New...