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JP89 (DIN-DOUT) - Router


Phatline
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The Idea is:

have a Main Userinterface - which is connected to the Core Module via J89 (din dout shiftregisters).

but i want to remote more then one Core-Module with one UI --- nope i dont want to use mid) --- because on some later point i too want to switch the a bunch off SSD1306 ...

 

First i need a switching logic.

2 Buttons - to select the core module. these 2 buttons are connected to a counter, that can count from 0 to 7.

The counter logic should have 8 outputs, and only one output should be active at one time  > the one output that is counted/selected.

 

Connected to this 8 Outputs (which can be low or hi) are 8 switches, which are connected on one side to the 165/595 line (incl a buffer i guess?) - and on the other side to the 8 cores.

 

The counter logic itself is buffered so i can get its outputs trippled:

i need it once for the thing above (J89 switching) -

and second to have a HI-LO-Pin for  8 cores (connect to J10) - which activate and deactivate the input sense, and inital routines off the core module (custom code in there...) . - which i guess could make some troubles while switching (DIN activity... delay JP89 swithing possible? so the input sense status comes first? how?)

and third for 8 LEDs where only one is Active (indicate the choosen core)

 

the whole things should be designed in kicad for eurorack pcb... produce on jlpcb,  smd, and non exotic parts...

 

 

Any Hardware ideas? (74 logic? chips, op amps, examples, ore already existing modules ore circuits?)

Edited by Phatline
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@ Switch Delay:

The Databus Delayed-Switching could be made with a simple Capacitor charge - Schmitt trigger circuit (opamp, Electrolytic cap).

while keep un-delayed switching for COREs to be informed to stop looking on DIN-Ports

Edited by Phatline
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It's not quite clear to me what you want to do? You want to have one J89 SRIO chain and switch between several Cores?

If that's right, it is trivial to make a Johnson counter/decade counter out of a 4017 chip. You could think to use the output enable pin(s) of the buffer (541 or 125) that is used to interface the buss to the core. Each Core gets one buffer with the datalines connected to the inputs (+DIN to an output), the outputs are common to the J89 chain (+ the serial in). Advance the counter to "turn on" one chip.

image.thumb.png.3279a22ac3286d2ab7e03658211ed440.png

 

Edited by latigid on
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Okay, all good then! Above schematic is wrong of course as the "SI" pin from the chain should be connected to the input! But you get the idea I hope.

Actually, the SI normally comes in unbuffered and only SC/SO/RC1/RC2 (outputs) are buffered. But for your case I think you also need to "switch" the SI? So you can use 5 gates or just combine RC1/RC2 as they are normally set simultaneously 

Edited by latigid on
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I didn't check in great detail but that seems to be the right idea. The delay part didn't really make sense to me.

I think that you also need to consider how to avoid activating >1 line at once.

As an alternative idea, why not program a 595 shift register to send out the required "single" signal? You could easily scan in switches (momentary buttons) to specify the active line and output one 0/LO out of 8 outputs. You could also have a cycle button.

Note that outputs are high impedance (i.e. disconnected/floating) when the /OE signal is high. This means that you must define the logic level of all downstream logic inputs with pull-up/-down resistors (1k-10k), whatever the default state should be.

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8 hours ago, latigid on said:

The delay part didn't really make sense to me.

i made a video  (and cut it - in real it was twice long...)- that explains the whole thing - and why a delay - i think is needet:

 

Quote

I think that you also need to consider how to avoid activating >1 line at once.

delay?

 

Quote

As an alternative idea, why not program a 595 shift register to send out the required "single" signal? You could easily scan in switches (momentary buttons) to specify the active line and output one 0/LO out of 8 outputs. You could also have a cycle button.

i dont get this idea.

 

Quote

Note that outputs are high impedance (i.e. disconnected/floating) when the /OE signal is high. This means that you must define the logic level of all downstream logic inputs with pull-up/-down resistors (1k-10k), whatever the default state should be.

I will do that thanks!

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Posted (edited)

... a other thing... i get my head by switching the J15A Ports... this are already buffered  signals on the core? do i have to route them - or is it enough to connect them somehow together (and pull down), and just tell the cores to shut up, and only one to speak?

i ask, because, J15A connected to 8xSSD1306 need 10 Data pins (CS1-CS8, SC, SD) a 74HC541 has only 8 Buffers (and i did not find a buffer that makes more then 8), by switching 8 cores i end up by 16x Buffer Chips... that is to much place-usage (eurorack...), and i have the feel (not the knowledge) that a output is not so crucial... since i will initialize the Screen-Driver anyway while the program is running...

 

addet the Pull-Down Resistors

SRIO-ROUTER-shem.thumb.jpg.1719a3eb0ea0ba1061982cd0a5c52982.jpg

 

, and separetet to 2 Boards ( 5x10cm each) (the lower is the Switch board (counter), the uppter the J89-Switch Board

SRIO_ROUTE-PCB.thumb.jpg.dcb860318710c110334b11fd2991071f.jpg

 

startet a wiki - so i did not have to search for the BOM twice.... SRIO-ROUTER

Edited by Phatline
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14 hours ago, Phatline said:
23 hours ago, latigid on said:

The delay part didn't really make sense to me.

i made a video  (and cut it - in real it was twice long...)- that explains the whole thing - and why a delay - i think is needet:

The "realtime switch" makes more sense now. I thought you meant you had 8 individual switches to pick the core directly.

 

 

14 hours ago, Phatline said:
Quote

I think that you also need to consider how to avoid activating >1 line at once.

delay?

If it's controlled by the counter, then I think only one line can be activated at once.

I don't think you really need the delay lines. If the run state chosen by the counter is fed to the Core, when the state changes you could run a wait timer to ignore incoming inputs, also to delay sending more data out.

 

14 hours ago, Phatline said:

 

Quote

As an alternative idea, why not program a 595 shift register to send out the required "single" signal? You could easily scan in switches (momentary buttons) to specify the active line and output one 0/LO out of 8 outputs. You could also have a cycle button.

i dont get this idea.

A 595 shift register has 8 outputs, so in theory you can write a program to choose the output instead of cycling through the counter.

 

6 hours ago, Phatline said:

... a other thing... i get my head by switching the J15A Ports... this are already buffered  signals on the core? do i have to route them - or is it enough to connect them somehow together (and pull down), and just tell the cores to shut up, and only one to speak?

i ask, because, J15A connected to 8xSSD1306 need 10 Data pins (CS1-CS8, SC, SD) a 74HC541 has only 8 Buffers (and i did not find a buffer that makes more then 8), by switching 8 cores i end up by 16x Buffer Chips... that is to much place-usage (eurorack...), and i have the feel (not the knowledge) that a output is not so crucial... since i will initialize the Screen-Driver anyway while the program is running...

I think you need to buffer/switch them, otherwise the clock lines etc. will interfere? 

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