x0x style seq... Need hardware help (LONG post!)

[stryd_one]

Hey all  :D

Short version:

I need help with building hardware to interface a core module with SRAM.

Very long version: (sorry!)

I'm back from the dead ;) Some of you may remember that I was working on an x0x (rm1x/electribe/schaltwerk/whatever) style sequencer before I disappeared, and I must admit that I'm very surprised that someone hasn't given this a shot while I've been gone. I see that there is still much interest in this idea, however as the design would branch away from the standard MBHP/MIOS design, progress seems to come to a halt.

I've moved house (just 4000km's away), left behind a lot of things that have been in my way, and got a great job with great pay... So I want to make hay while the sun shines. I've done lots of work on the design and inner working of this thing, theres a stack of code and pseudocode and notes and half-made stuff. I'm fairly sure I can make this work with a single core module now, but there is one issue that I just can't seem to solve. RAM.

The way I see it, there are several available solutions:

1) Newer PIC - eg 18F4525 - This PIC is pin compatible with the 452, will need some minor code changes to work, but has 4 times the RAM onboard. This is nice, but I don't think that it will be enough.

2) New Core Module based on FPGA - eg cyclone - LOTS of work! If others were interested in helping out a LOT, I would do this, but otherwise it may be too much work for me alone. I'm sure TK is too busy for this and he should be involved in any such project. So maybe this is out of the question.

3) External SRAM - There has been talk of this in the past. TK was even kind enough to suggest pin wirings and a suitable chip :)

I'm very confident that I can deal with all the code, but hardware is not my strong point.  What I am hoping is that someone here knows enough about the hardware side, to design a board with more RAM that will work OK so that I can do the code. I will be happy to pay for any hardware required to make the board if you can get this to work.

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Some notes from TK on SRAM:

For common SRAM chips a lot of connections have to be made: i.e. a 128k SRAM needs 17 address lines, 8 data lines and 3 control lines... the number if wires could be reduced by using a latch like known from 8051 devices, and the data bus could be shared with the LCD bus --- but this would result into a design far from the (easy-to-solder) MBHP

.......

So long most pins are free, you could hook a 128k SRAM (like the 628128 ) to the core directly - here an example:

data lines could be connected in parallel to the LCD port, 8 address lines could be multiplexed with the data lines like known from 8051 designs (by using a 74HC573 latch)

8 additional address lines could be connected to J5

the remaining address line to J7:RC

the chip select to J7:SO

the latch enable to J15:RS

the R/W to J15:RW

You need to implement a (simple) read and write routine for RAM accesses (RAM_Write, RAM_Read) and put it into your application. The resulting access time should be about 2 microseconds (ca. 20 instructions) - fast enough for large data structures.

SRAMs can be buffered with a small 3V battery

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Is it really that easy?! Do I need to add anything else (pull up/down resistors or caps or something)?

How about J6 (AIN) and J10 (SID)? Analog ins and MBSID won't be supported by the seq, can I use those? I can check the datasheet to see if the port is compatible, but I hope that someone here knows, so I don't have to read that darn PDF for hours (again) ;)

It would be great if this could be made into a kind of Core Module 'daughterboard', which would allow normal a core module to be used, and then the new module with the SRAM and latch IC's piggyback on top of that, and then LCD module etc from there. This will keep the project much closer to the MBHP project design. (even thouh the software may not be 100% MIOS compatible)

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For those who haven't read about my ideas over the last years:

Once I can get the SRAM to work, a little programming will result in something like a shaltwerk / zeit / phaedra / fruiyloops interface, mixed with the awesome but now apprently extinct ( :'( The link died in the last 48 hours) Signal Arts Performance Seqeuncer and the Manikin Schrittmacher.  The idea is to have independent tracks of independent play speeds and lengths, which can trigger either MIDI stuff such as notes or CC's etc, or they can be used to trigger other tracks, manipulate other tracks' play speed and length, manipulate note/velocity/cc/gate length values and mutes in other tracks, or even within the same track. It's basically a semi-modular sequencer. Think of a kind of hardware version of Five 12's Numerology.

The UI would consist of (among standard things like menu buttons and jogwheel and LCD etc) a scanned matrix of 8 steps by 12 tracks. The reason for choosing 12 tracks is to allow a matrix editing mode where one track can be expanded to take up the whole button matrix. This will allow a whole octave of notes over 8 steps. Obviously this mode will have octave up/down buttons.

There would be no song modes or pattern chaining etc as a separate section, instead just normal tracks can be used to sequence other tracks in order.

For example, Track 1 of 4 steps, plays at 1/4 master tempo. Steps 1, 2 and 3 play the drum break programmed into track 2. Step 4 plays the sequence in track 3, which has a drum fill programmed into it for the end of the bar.

Meantime, track 4 with 2 steps plays at 1/4 the speed of track 1 (1/16th of master tempo). This track changes the trigger on step 4 of track 1, so that a different fill is played at the end of each set 4 bars.

You could have track 5 playing a 5 step pattern at 5/4 speed - polyrhythms. These five steps will loops in sync with the 4 step tracks above.

You could have track 6 playing a 5 step pattern at master tempo - polymeters. This way, 4 steps will play for every 4 beats at master tempo. The 5th step plays at the same time as the first step of the next loop, the 2nd step of the next, the 3rd step of the next, Every 20 beats, the two loops will start together.

I would also like to include an 'envelope' mode where steps act like envelope breakpoints for midi cc's or NRPN's etc, various MIDI FX (gaters, delays, etc) and an arp/transposer. This is one of the few things I haven't actually tried to do yet so no promises :)

You can of course take this concept much further by doing weird (silly) things like, uhmmm, playing a 13 step track at 3 times 7/5 of master tempo (21/5) which triggers another pattern to move backwards and forwards step-by-step (say 3 steps forward, then 4 steps back, then 2 steps forward, then 5 steps back etc) through a pingpong loop, on which each step changes the loop mode of another pattern at 63x master tempo which controls the start point of a reverse loop which changes the breakpoints of an envelope sending MIDI CC's to do filtersweeps on your MBSID  :P Or something stupid like that ....

There are other things too but this post is already WAY too long  :-\

Please feel free to send me any ideas you have which you would like to see included, or to volunteer help :)

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Regarding the Zyklus MPS: (and Vangelis Direct)

I only just discovered this today (I've been researching this subject for years and somehow missed it) while reading posts from while I was away. Guys, you were looking for a manual for the machine, you can find it at:

http://www.vyla.co.uk/

You'll also find the preliminary spec for a new sequencer called the Improvisor. Just in case anyone is thinking "Hey, this stryd guy is stealing the idea", start searching this forum and find my ideas for this being expressed over 2 years earlier :) And the ideas are much older than that.. I say this because I do not want people to think I am stealing :)

Congratulations if you made it this far!!!!!  ;D

[TK.]

Hi,

Is it really that easy?!

yes, it is :)

Do I need to add anything else (pull up/down resistors or caps or something)?

not really, but bypass caps make always sense as we learned some days ago...

How about J6 (AIN) and J10 (SID)? Analog ins and MBSID won't be supported by the seq, can I use those?

yes, the only exception is pin RA4 which has an open drain driver and requires a pull-up. All other pins are (sometimes optionally) working with a TTL driver. See the j5_dout example how to use the analog pins as analog outputs

Best Regards, Thorsten.

[stryd_one]

Hi,

yes, it is :)

TK .... You're the man :)

[TL]

data lines could be connected in parallel to the LCD port, 8 address lines could be multiplexed with the data lines like known from 8051 designs (by using a 74HC573 latch)

8 additional address lines could be connected to J5

the remaining address line to J7:RC

the chip select to J7:SO

the latch enable to J15:RS

the R/W to J15:RW

Wouldn't it be easier (and maybe even faster) to use D0-D7 from the LCD for both the address and the data lines of the SRAM using 2 Latches for the address lines?

Since it simplyfies the connection of the SRAM module to the core (only 8 Connections from RB0-RB7) and some pins of J5 for ALE of latches, the remaining address lines (A17), R/W, etc.

And it would simplify the calculation of the address bits to output: take the low byte (D0-D7)of the SRAM address put it in the first latch, put the high byte (D8-D15) of the address to the second latch, set some pin of J5 to the value of A16 and read/write the data to/from the SRAM.

If this would make sense, I could make a schematic the next few days...

[TK.]

Hi TL,

yes, this is also possible, but increases the latency from calling the data read/write routine and accessing the data bus. On such a complex sequencer project best performance is always desired.

However, I guess that schematics for both solutions would be interesting for Todd :)

Best Regards, Thorsten.

[stryd_one]

Hi TL,

Thanks for your input mate  :D I can't wait to see what might come next

Cheers!

[stryd_one]

Hey guys, I'm having a great deal of trouble finding datasheets for the 628128...

I read something about the 628128 being 'end-of life' (discontinued)... I did find some info for the 628512 which has a few more pins but much more RAM. There are enough pins on the core to drive one of these though... We still have J10 and J4 :)

I can't find either chip in eagle though... Am I doing something wrong?

Sorry to ask so many questions   :-[

Todd the n00b

[TL]

http://www.hynix.com/datasheet/pdf/sram/HY628100B(Rev12).pdf

Cross reference list:

• Hynix HY628100B
  
• Samsung K6F1008R2A
  
• Cypress CY62128V18
  
• NEC PD441000L-DX
  
• Toshiba TC551001C
  
• Hitachi HM628128D
  

[stryd_one]

Thanks man :)

I found it in Eagle too... For some reason the memory-hitachi tree was missing... I suspect it was "pilot error" ;)

[TL]

I've done a quick schematic

Download

It's not tested so I don't know if it works...  ;)

[moebius]

Hi,

One thing I have never figured out is - howcome these SRAM chips have Address and Data lines separated? No alternatives? And is the latch really needed? Really?

Bye, Moebius

[TL]

at least one latch is needed, because the core has not enough pins free to use for the address lines...

I think I will do the schematic Torsten suggested tomorrow...

Why address and data separated?

with the address lines a cell within the sram is selected and with the data lines the content of this cell is read or written.

Here is a short description who different ram types work:

http://arstechnica.com/paedia/r/ram_guide/ram_guide.part1-2.html

I hope my description and the link will help you...  :)

[moebius]

at least one latch is needed, because the core has not enough pins free to use for the address lines...

I think I will do the schematic Torsten suggested tomorrow...

Sorry? No enoght pins? For Addresses? Aren't SRAM address lines also 3-state, when not /SElected? Or whatever..

Thank you for this revelation - I could never had figured out this by myself! Do you know if the Cells are selected and the Data of the Cells are sent out - In the same time?

LIke - I could think of a SRAM with A/D mixed but some address enable line..

Bye, Moebius

p

[stryd_one]

TL that schematic looks great. I'm looking forward to seeing your next one too. Thanks again for your input :)

Would you mind if I look at the eagle files too? I'm trying to learn to use it.

Just a side note....

Look how many views this thread has! And in just a few days....Obviously the concept is a popular one :)

[TL]

For the 128k x 8 SRAM 17 address lines, 8 data lines and 3 control lines are necessary, makes a total of 28 pins.

And from the core schematic, RB0-RB7, RA0-RA5, RE0-RE2, RC0, RC1,RC4, RC5, RD5 and RD6 could be uses, makes 23 pins.

So at least one latch must be used.

Yes, these timings are explained in the datasheet.

Here are the 2 diagrams for read and write access:

Yes, a parallel A/D and SRAM could use most data/address lines together, but the A/D and the SRAM must use their own Enable lines...

[TL]

And here is the schematic of Thorsten's idea:

Download

Please keep in mind that both designs are a little bit simlified since the bypass caps are missing, which are important for the SRAM...

And I'm not sure about the use of J7 / SC, maybe another pin of the core should be used instead... Thorsten ?  ;)

[stryd_one]

Awesome TL. This is more complex in a way, but as TK said, perhaps it will be faster. The more I look at the schematics, the more I can see that you have put quite a bit of thought into this and I want to say thanks once more.

OK, so like... Not to try and pretend like I actually have a clue  ;) , but I've looked at the datasheets for both, and RC0 (J7:RC) seems to be a compatible pin for the job, and I don't think it will clash with any other MIOS operations...

Did I pass the test?  :D

[stryd_one]

OK, I give up... I've been trying to convert this thing to a board in eagle (I did my own schematic which is very much the same as the above)... Maybe it's meant to be difficult, but to make this a one-sided board, the best I've been able to do is to have 11 airwires!

Is it likely to be this difficult? Or is it just cause I'm a newbie?

Perhaps a double sided board would be more appropriate... But perhaps that makes it difficult to build, from a DIY point of view?

Maybe I should stop asking so many questions and leave it to those who know what they're doing... But I don't want to make you guys do all the work unless you want to.... That said, I'm happy to do all the coding work once it's made, so...... What do you think?

[moebius]

OK, I give up... I've been trying to convert this thing to a board in eagle (I did my own schematic which is very much the same as the above)... Maybe it's meant to be difficult, but to make this a one-sided board, the best I've been able to do is to have 11 airwires!

Is it likely to be this difficult? Or is it just cause I'm a newbie?

No, you're doing just fine ;) Routing memory busses on one-sided board is just pain-in-the-You know where. Airwires on any "more complex" designs are unevitable.

Perhaps a double sided board would be more appropriate... But perhaps that makes it difficult to build, from a DIY point of view?

Double-sided boards ARE doable from a DIY point of view - it just takes more patience and skills..  alignment between two sides must match really well. But routing a double-sided board is just so much easier task.

Maybe I should stop asking so many questions and leave it to those who know what they're doing... But I don't want to make you guys do all the work unless you want to.... That said, I'm happy to do all the coding work once it's made, so...... What do you think?

Pheww-- any volunteers?

Bye, Moebius

[d2k]

ez ekaf...

I'll have a go at the pcb....for some mios coding credits which will be needed in the future tho ;)

peesh

[TL]

Here is my first pcb design.

This is my very first pcb design, so I don't know if it would work in the real world...

Any comments about this are welcome...  :)

[d2k]

Well, here's another layout...single sided, 2 bridges (+5V/GND lines):

Had to change a few connex from TLs' original schemo in order to route without that many bridges...

[stryd_one]

:o

* Todd bows to his superiors *

;)

You've even put in the bypass caps!

Thanks guys! I think I better start coding!

(long pause while thinking) Hangon a sec, did you just call me ekaf?  ;D  How'd you figure that out?! hhehehehehehe

[d2k]

it's muted u loon  ;D

[stryd_one]

My cover is blown!  ;)

(for everyone else.... I know d2k from somewhere else on the net, never mind our shenanigans :) )