x0x style seq... Need hardware help (LONG post!)

[TL]

Great, d2k's board is much nicer than mine  ;D

Well, I guess I've to learn a lot...  :)

Please keep in mind the schematic is not tested at the moment.

I'm going to build one on perfboard and test it this week.

Unfortunately  I've to build a core module first ( all my core's are in my SID ) and wait for the PIC from Voti and the SRAM from Reichelt.

@d2k:

Would you mind to send me the changed schematic / board file ?

I would then do the documentation (create nice pdf's of the schematic and board, connection diagram) of this module after verifying the circuit works.

[stryd_one]

Oh yeh good point, can I grab the schem's too, I might need to know which pins go where if I'm gonna write the code :)

No rush at all, there's plenty to keep me busy  ;D

[Davo]

FWIW, 62256 SRAMs are fairly easy to find on Ebay.  A few months ago I bought around 60 of them for an unrelated homebrew project.  They're almost always pulls, but they work well and the price is good.

[TK.]

Yes, J7 is a good choice for the 3 remaining address lines

Best Regards, Thorsten.

[sjakie]

Hi Guys,

Wouldn't it be better to put the high address lines in the latch and dedicate the low address lines to port J5. This allows for really fast 256 bytes block reads I think.  (Of course this can be done in software without changing current design).

Just a thought ;)

[TK.]

Hi,

when you are using a SRAM, the address and data line assignments don't matter. So, it's on the user if he uses A0 or any other address input as LSB, therefore such "burst" accesses can be realized with any pin assignment :)

Best Regards, Thorsten.

[d2k]

Hey,

Havnt't been following this project to closely - but is this sram module spose to consume 1 whole core? If so, Smash had an idea to make it like a plug-on brd that just sits on the core - would be ideal eh :)

I think by the sounds of the last few comments some improvements can still be made no? So mightaswell wait till its 'go' to make a brd proto/upload files etc...

TL, PCB layout is a kinda voodoo science it seems and I don't understand 99.9% of it - my shit prolly only looks 'nice' as I'm from a graph design/page layout background - my 1st pcb was done in illustrator! (and was a mess looking back) ::) Been using eagle for a while now and liking it bigstyle - kinda like logic in terms of learning curve tho...perseverance n gui pokery needed.

Just thought - if a few dif types of ram can be used I guess it'd make sense to allow for this on the pcb too if possible...

[TL]

Hey,

Havnt't been following this project to closely - but is this sram module spose to consume 1 whole core? If so, Smash had an idea to make it like a plug-on brd that just sits on the core - would be ideal eh :)

Yes, I think this would be great.  ;D

I think by the sounds of the last few comments some improvements can still be made no? So mightaswell wait till its 'go' to make a brd proto/upload files etc...

Right. Hopefully my spare time (IT business is sometimes really a spare time killer  :P ) and missing parts will allow me to test it this week... ;D

TL, PCB layout is a kinda voodoo science it seems and I don't understand 99.9% of it - my shit prolly only looks 'nice' as I'm from a graph design/page layout background - my 1st pcb was done in illustrator! (and was a mess looking back) ::) Been using eagle for a while now and liking it bigstyle - kinda like logic in terms of learning curve tho...perseverance n gui pokery needed.

Thank you for your encouraging words...

Actually I'm totally new to Eagle...  ::) and yes I've learned the last 2 days a lot!  ;D

Just thought - if a few dif types of ram can be used I guess it'd make sense to allow for this on the pcb too if possible...

In theory this would be possible, II don't know actually if different sized of SRAMs are pincompatible in some way...

A few thoughts about using 2 latches ore only one latch:

Wouldn't it simplify the calculation of the address lines if 2 latches are used which are connected to RB of the PIC?

Just take the low byte of the address and put in latch 1, take the high byte put it in latch 2, put the remaining A16 line to one pin of  J5, and read/write to/from the SRAM.

Or is putting A8-A15 in the second latch eating more time than the software calculation and spreading the high byte to the 3 different ports RA, RE and RC of the core ?

Actually I'm relative new to PIC asm ( I've done a few things ace ages ago with 8051 derivates) and don't know about this point...  :P

Any statements? Maybe Stryd_one or TK ?  ;)

[d2k]

btw, would a lith batt be needed for backup +3 power?

[smashtv]

Just thought - if a few dif types of ram can be used I guess it'd make sense to allow for this on the pcb too if possible...

In theory this would be possible, II don't know actually if different sized of SRAMs are pincompatible in some way...

I'm thinking of a socket-stack type daughter card where you remove the PIC, plug the PIC and sram into sockets on the daughter board, then plug the board into the pic socket on the core.

That way we eliminate several issues:

Differences between the location of connectors on the various version(s) of the core.

No need for feedthrough connections for the LCD, etc.

Would work fine for people who have soldered wires to these pinheader connections.  (SIL sockets won't mate good with pinheaders that have been soldered too, even with all the solder removed the leftover tinning of solder would make a sketchy connection)

The only funky part needed would be a wirewrap 40pin socket.

Great to see more MIOS dev from someone besides TK!  ;) 

For some of us hardware is the easy part, coding is difficult, and for others the coding is easy but fighting with eagle for hours is not.

Anyone tempted to code anything MIOS should know that all the HW help you need is just a post away!

Smash

[sjakie]

As far as I know SRAMs use similar pinning as 128KB for 256 and 512KB (even for standard eproms and flash it is basically the same). The only PIN you probably shouldn't use is CS2 (e.g. connect to +5 with pull-up). It is used as a extra address line (a17) on bigger sizes. Pin 1 is also used for addressing on 512KB (a18).

Using latches would be more elegant and much more powerful, so if it doesn't matter for speed please do!  :P

It may be useful in that case to use a 3->8 decoder (74hct138 or 238) to control the latches and ram cs. That way there is room to put in even more bus type devices. Since 3 IO pins are already required for this setup, there is no extra 'cost', only gain :)

[TK.]

You are both correct: the performance penalty is not so high when two latches are used instead of one (however, burst accesses would take a little bit longer), also the 3->8 decoder could make sense.

Maybe you should also discuss if surface mounted chips are better for the "sandwich" method, where the SRAM module is stacked on the PIC

Here a circuit for backup memory (I used this ca. 8 years ago for a uC controlled preamplifier)

Best Regards, Thorsten.

[TL]

@TK:

Thx, I've searched already something like this but found nothing...  ;D

@all:

My current opinion towards the module:

• 
  
• 2 latches for addresses ( or maybe even 3 latches, this way 128k x 8, 256k x 8, 512k x 8 and even bigger SRAM sizes could be used )
  
• 3-to-8 decoder to drive the latch enables, etc.
  
• battery backup
  
• the same board layout for different  SRAM sizes (e.g. 128k x 8, 256k x 8 and 512k x 8 )
  
• design the board as piggy-back for the core module
  

Comments ?  ;D

[TL]

Additional note:

It seems that2mbit SRAM ( 256k x 8 ) is not available in 5V, only in low voltages...

128k x 8 and 512k x 8 is available as 32-DIP, 32-SOP and 32-TSOP2 packages...

[moebius]

Additional note:

It seems that2mbit SRAM ( 256k x 8 ) is not available in 5V, only in low voltages...

Don't believe you.

Bye, Moebius

[stryd_one]

I've created a monster!  :o  It's alive! ALIIIIVE!!  Heheheh *tightens the bolts in his neck*

As for the chips availability, I must admit it's surprising to hear the middle range chip is only available in low voltages, but that's not really important, we can just ignore that model if we are going to make this thing work with different chips... Making it work with different voltages is not something I'm really interested in. Too hard basket!  ;)

TK, thanks so much for the schematic of the battery backup, as was said, that is hard to come by. Thanks for sharing yet another little gem with us.  :)

I'm not sure as to the benefits or drawbacks of SMD chips... anyone?

Smash, I REALLY like the idea you have for the implementation of the daughterboard!

Another advantage which you didn't mention is that by doing it in this way, we can in theory also make any and all of the pins on the PIC available for driving the SRAM. This has the advantage of making it far easier to support different types and sizes of chip, in combination with 1,2 or 3 latches to allow I/O with the core module

Of course, if it is done in this way, it means that the latches will "switch" between working with the SRAM, and working with the interfaces on the core modules (AIN/OUT, DIN/OUT , LCD etc). This means that we would have to make some choices about performance.

The whole thing becomes a matter of a performance and flexibility trade-off... The more SRAM chips we would like to support, the more pins from the core need to be dedicated to the SRAM, the more latches need to be used, which results in slower access to the SRAM and to the core's I/O to other modules...

This is a difficult one... Where do we draw the line? Is it worth supporting many different SRAM types, if the core becomes so bogged down driving them that it becomes less useful for driving the core I/O?

[d2k]

Creating a lil psu for the +3.3V isn't a biggie...

[stryd_one]

Oh I agree, but I just don't know if it's worth the effort... Maybe I'm just lazy ;)

I'd rather invest the effort in including one more address line and just using the larger sram... Easier, and far greater benefit...

[cheater]

Let's have the core module support at least 25 different ram types. The PCBs should have sockets for each type of packaging of each of the ram types in each size. We'll also need several voltage levels there. Please?

Also, I want it to control my fridge.

Seriously though: there's a reason why MIOS is only available (officially) for one type of PIC.

[TL]

According to the datasheets it's no problem to support 128k x 8 and 512k x 8 SRAMs.

I've updated my schematic already and after I verified it works I will publish it here and maybe d2k could create a pcb ;)

My design uses 2 latches, the remaining address lines go directly to the PIC,a 3-to-8 multiplexer to control the latches and has a backup battery.

SMD vs. DIL topic:

I think DIL is much easier to solder for most DIY people...

[stryd_one]

Cheater: ehehehe you obviously see my point ;)

Guys, although I want to make this solution flexible for the needs of all people, I do wonder if it is worth all this effort and performance drops. I'm sure TK would have liked to have a 68000 core module or an atmel core module, and although there are strong arguments for it, the PIC does the job and so there's not really a need for it.

If we can make a 512x8 or 256x8 SRAM work, why do we need to support a smaller chip? The price difference seems to be only a few dollars at most, the equivalent of a single knob for a pot.. If you only need 128k, then just don't use the rest :)

TL, thanks for doing this for us. I would really like to keep the latches down to 1, so as to enable burst transfers as discussed earlier - Perhaps you could use the same schematic as your earlier model of TK's idea, and use J10 for the extra address pins to support 512x8?

Does your new schematic encompass smash's idea of having this be a plug-in board?

[smashtv]

I've updated my schematic already and after I verified it works I will publish it here and maybe d2k could create a pcb ;)

I'm not positive but I think d2k passed the pcb layout chores on to me, but that's no problem except for time (I'll be out of town from tomorrow night until the weekend).  TL if you want a look at what I have in mind send me a copy of the most current .sch and I'll knock it up as a "throw-away" design, meaning this is just a preliminary design to look at (proof of concept) but -not- etch, as there might still be needed changes or errors in the design.  Or I can wait until the weekend or for your final .sch, your choice.  ;)

Does your new schematic encompass smash's idea of having this be a plug-in board?

No need, send me what you have and I'll do the math..... :)

On multiple chip support:

Pick one chip based on these criteria, in this order:

1) availability

2) performance

3) price

In other words pick the one that makes the most sense, if others are pin compatible cool, if not no big deal. 

I can do variants for as many different ram chips as you guys can make .sch files for if they are really needed.....

Let's have the core module support at least 25 different ram types. The PCBs should have sockets for each type of packaging of each of the ram types in each size. We'll also need several voltage levels there. Please?

Could you please be a little more sarcastic without offering any real help?  Please?

Sarcasm here makes people scared to post (who wants to be flame bait?) and is difficult for people struggling with english to understand.......

I still love ya but this is not synth-diy and we -will- keep it fun here.....  ;)

Best!

Smash

[stryd_one]

I think maybe the humourous tone in cheater's post was lost... Or maybe I'm just a little too light-hearted and he was really being malicious... But I think for the sake of friendly conversation I will assume he was being funny.... WEREN'T YOU CHEATER!!! WEREN'T YOU!!!!!!!!! [move]twisting your arm[/move] ;D hehehe

hey cheater next time use one of these:  ;)  ;D

Smash, I reckon you're right on the money. Availability/performance/price. Now I will openly admit that I have no clue on how to find these things, aside from searchin on ebay :) (PS no hits at all on any of the SRAM types, darn.)

I'll let the pro's make the call as to which chip is the one to go for. Obviously the bigger the better.

Also, thanks for taking on the work of PCB design smash. There is absolutely no rush and no pressure, do this in your own time. We are lucky to have you show such generosity at all, and I'm sure noone will rush you.

WILL YOU? WILLL YOOOOU!!!??? ;D

heheheheheheh

todd...who just can't seem to act serious!

[stryd_one]

How's this:

http://www.futurlec.com/Memory/684000pr.shtml

I looked on farnell and some of the chips of this size were about $80-100 !!!

I'm sure I'm missing something as usual.

Todd the hardware dummie  ::)

[stryd_one]

I just came across this link:

http://www.infinityelectronics.com/crossref.htm#sram

thought it might be handy