jbdiver Posted February 15, 2013 Report Share Posted February 15, 2013 I'm finally testing my aout_ng board and running into a problem. Basically, it's not generating any cv's. Here are the troubleshooting steps I've taken: 1) The board seems to be getting proper power. +5 is coming from the seq4 and +/-12 is coming from eurorack power. Aout_ng led lights up. I read proper voltages between pin 4 & GND and pin 11 and GND on IC3 and IC4. 2) I can pass data signals from the seq4 to the board. I used the "testaoutpin" command in MIOS studio to set CS/SI/SC. The only anamoly I noticed here was that when I set CS & SI to 1 the voltage reads about 4v whereas setting SC to 1 reads 4.9v. All three pins reset to about 0.11v when set at 0. 3) I'm not 100% sure I have the data lines connected properly to the aout_ng -- hopefully someone can confirm. When I ran the testaoutpin command here is how J1 on the aout_ng was connected to the seq4: 1 - GND (Vs) 2 - +5v (Vd) 3 - CS 4 - SI 5 - SC 4) I configured a track to use the aout interface, channel 1. I sent a series of C-3 notes. The buffered gates are working perfectly. I see no voltage change on CV1. Board was built with bipolar option, but all channels are set to unipolar for now. Any recommendations for the next troubleshooting steps? Quote Link to comment Share on other sites More sharing options...
Altitude Posted February 15, 2013 Report Share Posted February 15, 2013 how long is your cable between the core and NG? I had problems getting mine running when the cable was more than a foot. Keep it under 10" Quote Link to comment Share on other sites More sharing options...
jbdiver Posted February 15, 2013 Author Report Share Posted February 15, 2013 The core is connected to my db25 output/buffer board, 24" serial cable, my db25 input board, and finally the aout_ng. The total length is probably 3ft. I'm taking voltage measurements at the very end of this connection chain. The signal strength doesn't seem to be an issue. I'm open to suggestions of how to verify this. I'm not sure how a person could make an external aout configuration much more compact. I have 6" of internal cable just to connect the core to the db25 on the back of the seq4. Quote Link to comment Share on other sites More sharing options...
latigid on Posted February 16, 2013 Report Share Posted February 16, 2013 Perhaps you can test the IO transfer by connecting J19 (without the buffer board) directly to the AOUT module? Quote Link to comment Share on other sites More sharing options...
TK. Posted February 16, 2013 Report Share Posted February 16, 2013 1 - GND (Vs) 2 - +5v (Vd) 3 - CS 4 - SI 5 - SC Just to be clear, the connections to J19 are: J1:1 -> J19:Vs J1:2 -> J19:Vd J1:3 -> J19:RC1 J1:4 -> J19:SO J1:5 -> J19:SC In addition, the AOUT_NG interface has to be selected in the CV Configuration menu (by default, the AOUT module is configured) Best Regards, Thorsten. Quote Link to comment Share on other sites More sharing options...
jbdiver Posted February 17, 2013 Author Report Share Posted February 17, 2013 Okay, here's an update. I verified that my pin connections were correct. I created a short cable to connect the core directly to the aout_ng -- bypassing the two little connector boards and serial cable between these modules. When I first tested this direct connection it didn't work. The module did not generate CV's. I hooked the seq4 back up to my computer to run MIOS studio "testaoutpin" tests on the cable to make sure I was using the right pins. Then I noticed the "testaoutpin reset" command. I issued this command, turned off the seq4, and hooked it back up to the aout_ng module. Success! The seq4 generated proper CV's (at least on channels 1-4 that I tested). Thinking that the reset command potentially fixed my problem, I hooked the two connector boards and serial cable back up and tested the aout_ng again. No CV was generated. Bummer. My testing confirms that I have a working aout_ng module. It's just not working with my boards and serial cable. I'm 99% sure the signal paths on my connector boards are correct since I can generate the proper testaoutpin signals at the end of the signal chain. The voltages look the same whether I'm using the "long" signal path or the direct connection to the core. Am I running into the dreaded cable length issue? Anything I can do to mitigate this problem? I'm using the shortest serial cable I could buy. The success of my project is based on the ability to install the aout_ng module behind a eurorack module. Thoughts? Quote Link to comment Share on other sites More sharing options...
grizz Posted February 18, 2013 Report Share Posted February 18, 2013 When I get the board that you sold me I will test it out... I have to order parts first though. I have had similar problems with my stm32, and I'm hoping that your breakout board solves them. My understanding is that with the breakout board cable length is no longer a problem because it is converting the 3.3v to 5v. alex Quote Link to comment Share on other sites More sharing options...
jbdiver Posted February 18, 2013 Author Report Share Posted February 18, 2013 Alex, quick clarification. I had no problem generating gate signals using my boards and serial cable. I only had problems generating CV's. The cv data signals are passed straight through from the core to the aout_ng module whereas the gate signals go through the buffer circuit. I'm reading the exact same voltages on the cv data lanes regardless of whether I connect directly to the core32 or go through the boards and serial cable. My next troubleshooting step is to replace the serial cable with a couple of short wires to see if the cable length really makes a difference. I'm not sure what else to try at this point. Quote Link to comment Share on other sites More sharing options...
jbdiver Posted March 16, 2013 Author Report Share Posted March 16, 2013 Quick update. I gave up trying to get the stm32 core to work with the aout_ng module. I got it to work intermittently. Following grizz's advice, I replace my core with the LPC17 core board. Success! I can start building the eurorack module now. Quote Link to comment Share on other sites More sharing options...
latigid on Posted July 15, 2013 Report Share Posted July 15, 2013 Just a thought here: J19 on the LPC core is already buffered, while on the STM 32 it isn't. This might make all the difference! Also, the pinning seems to be a bit inconsistent: J19: Vs Vd So Sc Rc1 J1 : Vs Vd So Rc Md TK : Vs Vd Rc1 So Sc The J19-J1 pinning is therefore not 1:1? Quote Link to comment Share on other sites More sharing options...
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