Large Shift register chains with MIOS32

[Duggle]

Hi there,

Ive developed a16 colour (using red/green tricolour LED) linear display strip. It features 4 i/o bits per LED. (Off, plus 3 levels of Red, 3 levels of Green, 3 levels of Orange, 6 in-between shades of orange)

The linear strip is designed to be mounted above/behind a midi keyboard key array. Possible display modes include noteon/off monitoring and showing the position of keyboard splits and zones.

Anyhow, once tested this will all be documented on my midibox blog.

One octave requires 6 shift registers. I have drafted a strip module pcb design that covers one octave. As many octaves as required are chained together. For my own use will be 2x4 octave (2x48 notes) in 2 strips.

This adds up to 48 shift register chips.

So my question relates to the maximum number of 74hc595 that can be chained. I understand it is the capacitive load of SCLK and RCLK signals to each chip that creates the limit.

Possible strategies:

1) Reduce the clock frequency of the SPI port. (Using DMA, this should have a very minimal, or negligible adverse effect on performance and is the preferred solution). Question: Where (in MIOS32) is the sr clock speed defined?

2) Provide a (stronger) buffered output to SCLK and RCLK (a buffer line driver at the start of the chain to drive these signals harder than the STM32 with pullup resistors.) Question: suggested device?

thanks

[TK.]

Hi Doug,

So my question relates to the maximum number of 74hc595 that can be chained. I understand it is the capacitive load of SCLK and RCLK signals to each chip that creates the limit.

Possible strategies:

1) Reduce the clock frequency of the SPI port. (Using DMA, this should have a very minimal, or negligible adverse effect on performance and is the preferred solution). Question: Where (in MIOS32) is the sr clock speed defined?

It's hardcoded in mios32_srio.c, but already configured for the lowest frequency.

However, reducing the clock rate won't allow you to extend the chain, because the impedance is the parameter which limits the length!

A refresher (I wrote about this multiple times in the forum, therefore only the reduced summary):

See this snapshot (measured on a PIC with a superlong SRIO chain, but for STM32 it would look similar):

The transients on SCLK line overshoot VH/VL, this will lead to non-deterministic clocking of the serial registers.

For STM32 the situation is even more critical if SPI pins are configured for push-pull mode, where signals are working at 3.3V

Therefore I decided to configure the pins for open drain mode, and to pull the signals to 5V.

This results into such sexy curves:

But experiments showed me, that the Logic-0 and 1 get above/below the threshold levels of the HCT chip family once more than 20 DINs and DOUTs are chained.

2) Provide a (stronger) buffered output to SCLK and RCLK (a buffer line driver at the start of the chain to drive these signals harder than the STM32 with pullup resistors.) Question: suggested device?

Yes, using buffers will cost you some additional chips, but it will help.

Take care that SCLK/RCLK have to be buffered separately for DIN/DOUT chain.

And buffers should be integrated along the chain, don't use starlike wiring, because this can result into setup/hold violations caused by unbalanced delays between FF clock and input!

Buffer IC: I tried a 74HC541 some time ago - it works, but has more buffers than really required (as mentioned earlier, starlike wiring, resp. using one buffer IC to distribute the SCLK for all DIN/DOUT chips is not recommented)

There are probably similar chips with lower pin-count

If you've SMD soldering experiences, such an option would be preferred

Best Regards, Thorsten.

[Duggle]

Thanks Thorsten,

I suspected this subject has been dealt with but forum searches including google search of the domain didn't help me find it.

Good to know regarding clock settings (already optimized), so I'll look at signal integrity.

I have a good CRO (like yours actually) and some experience in this area.

I think Ive decided to take the plunge and fabricate my design, knowing that there may be some tinkering to get a long chain to work reliably.

I can experiment with a level shifting buffer/driver, and passive termination schemes.

I can retrofit SMD buffers to each PCB if I have to. The worst case scenario would be to use multiple outputs from the STM32 to drive smaller chains.

[TK.]

Some informations are located in the hidden programmers section:

Some others in a german thread:

therefore you haven't got useful hits with the search function.

Please keep us updated - you could create a blog to document your experiments, this would result into a handy link for me to give other people some more informations about this topic.

I keep my own documentation effort low by setting the "not more than 16 DINs/DOUTs" rule ;)

Yes, using multiple SPI ports would solve this as well.

Best Regards, Thorsten.

[julienvoirin]

why not using BLM 16x16 matrix ?

[Duggle]

Please keep us updated - you could create a blog to document your experiments, this would result into a handy link for me to give other people some more informations about this topic.

Indeed, this is my intention. I'm having a pcb fabricated so a few weeks before I post anything.

why not using BLM 16x16 matrix ?

There are a few reasons:

• Matrix wiring is a bit messy for a long narrow strip ("linear"). The way I'm using it is one LED beside each midi keyboard key. The pcb is 20mm wide.
• Flicker free, full brightness.
• 4 bits per LED (16 "colour"), could be achieved with a matrix, but even more wires!
• Low cost and size of SMD HC595, makes it a neat solution (once signal integrity is guarranteed:-)

[Duggle]

Well, Ive added a blog article on my experiences with the long DOUT chain.

TK, the waveforms I'm getting from the DOUT SCLK of the STM32 are very different from yours. I get a full swing of about 0.5V to 5V and a very fast falling edge. It seems quite different from the waveforms you posted (the"sexy" ones).

I dont have a large number of MBHP DOUT PCBs to test this but I'm interested to see if the "working solution" works for traditional MBHP DOUT chains with both STM32 and PIC. It may be that the parasitics are a lot worse with the traditional layout.

I've made the MKLD pcb double sided with ground plane for low inductance etc. I plan to post info on this project as I develop it further.

[TK.]

Thanks for doing these experiments!

In my snapshots I connected the DOUT/DIN modules over a very long cable (ca. 3 m) to increase the impedance.

Normally I'm only using these snapshots to illustrate what I mean - the waveforms will always look different depending on the environment and the point from where the signals are probed.

(e.g. interesting is a comparison between SCLK at the core and SCLK at the end of the chain by using two scope channels)

Best Regards, Thorsten.

[TK.]

After I read the blog and want to thank you for starting this report! It makes the signal integrity issue better understandable and will help us to give newbies some arguments, why SRIO chains are usually limited to 16 shift registers (longer chains could require expert knowledge and technical equipment to get stable transfers)

There are two points I would like to add:

• we get a more difficult situation once a DIN chain is clocked by the SCLK signal in parallel to the DOUT chain: parallel chains can result into two "ringings" (one from the DOUT, one from the DIN chain - if they have different lengths resp. impedances.
  The situation will become even more difficult if DIN/DOUT registers are connected to SCLK in mixed order, in this case it can happen that the serial data won't be shifted correctly anymore due to setup/hold time violations caused by unbalanced clocks (with different delays) at SR inputs.
  This results into the effect that bits could be missed or added in the DIN and/or DOUT chain at random moments and positions (-> flickering LEDs, random button events) - this effect could vanish if you put your finger on the SCLK line (see also next point)
  
• by probing a signal with your scope you will add a capacitance to ground of ca. 10..100 pF (so far I remember, the value could be wrong or different for your scope). This has to be considered while comparing waveforms with theoretical calculations.
  This means in other words: currently your waveform looks nice, but once you remove the probe the "untouched signal" could be bad again. You won't see it (as you removed the probe ;))
  Seppoman recommented AC termination to solve this - it works! E.g., at the end of the chain add a 100R +100 pF to ground (so far I remember, meanwhile he even prefers higher capacitances)

Best Regards, Thorsten.

[Duggle]

• by probing a signal with your scope you will add a capacitance to ground of ca. 10..100 pF (so far I remember, the value could be wrong or different for your scope). This has to be considered while comparing waveforms with theoretical calculations.

Yes, there is interaction with the measurement, sometimes detrimental or otherwise. For example I found the ringing improved significantly by using a 10:1 probe setting rather than 1:1. I gather that this reduced the capacitance of the probe lead due to the divider in the probe. i.e a higher divider ratio means less capacitance, a more "objective" measurement. In this case the ringing wasn't as bad as it first looked.

I have to consider that the signal integrity issues I've come up against so far have not been bad enough for my DOUT setup not to work! I need to follow up with longer chains and ribbons to force the issue!

With the SCLK of only 500kHz I feel that we should not have transmission line problems. It requires further quantification and calculation. If slowing the clock edge rise time to say 100ns does not violate timings (it certainly tames ringing) and given that propagation delays are ~7ns/m should not cause problematic clock skew, the situation is hopeful. I need to model (on paper) the scenarios of DIN and DOUT chains and their wiring to convince myself thoroughly on this. Like I said Its a "feeling" based on the overall situation. I'll look into it.

The issues you mention, in relation to community based projects (guiding newbies etc) where only the lowest level of knowledge can be assumed and the range of configurations and applications is rather large, are challenging. One idea is to have a line driver on the core (or daughter board) that has jumpers to vary the source termination depending on the exact scenario. Could clock skew problems be overcome by assuming a constraint where DIN and DOUTs must be of equal physical length? (like those squiggly tracks on high speed PCBs, however I'm thinking of the ribbon wires that could be folded).

The 100R+100pF termination is interesting given that the characteristic impedance of ribbons is around 100 Ohm (with signal next to ground conductor on the ribbon). As I'm sure you understand, matching the characteristic impedance with a load at the end of the line absorbs the energy of the voltage and current waves thus eliminating the problematic reflections.

With specific regard to the AC termination mentioned, depending on the source resistance, it may also slow down the rise/fall time, also helping.

[TK.]

With the SCLK of only 500kHz I feel that we should not have transmission line problems. It requires further quantification and calculation. If slowing the clock edge rise time to say 100ns does not violate timings (it certainly tames ringing) and given that propagation delays are ~7ns/m should not cause problematic clock skew, the situation is hopeful. I need to model (on paper) the scenarios of DIN and DOUT chains and their wiring to convince myself thoroughly on this. Like I said Its a "feeling" based on the overall situation. I'll look into it.

btw. (I just remember that I haven't mentioned this yet): there is a topic which has to be considered when using serial resistors at signal sources for smoothing the signal edges: higher resistances will make the transmission line less robust against noise resp. they will worsen EMC.

In other words: a long transmission line acts like an antenna, and then higher the resistance between driver and logic inputs, than higher the danger that shift registers will get additional clocks (sporadically) in noisy environments (e.g. if you turn on/off another device)

The issues you mention, in relation to community based projects (guiding newbies etc) where only the lowest level of knowledge can be assumed and the range of configurations and applications is rather large, are challenging. One idea is to have a line driver on the core (or daughter board) that has jumpers to vary the source termination depending on the exact scenario.

I agree that it makes sense to add line drivers for the "next generation" core32 module. It will be at least a 100pin device, so that we don't need to consider different SRIO routing options - we can just use one dedicated SPI port for this and it never has to be changed (e.g. if I2S audio chips should be accessed as well)

We could even consider to add line drivers on each DOUTX4/DINX4 module - this would lead to the highest robustness and would also allow longer chains.

Could clock skew problems be overcome by assuming a constraint where DIN and DOUTs must be of equal physical length? (like those squiggly tracks on high speed PCBs, however I'm thinking of the ribbon wires that could be folded).

Yes!

Best Regards, Thorsten.

[Duggle]

btw. (I just remember that I haven't mentioned this yet): there is a topic which has to be considered when using serial resistors at signal sources for smoothing the signal edges: higher resistances will make the transmission line less robust against noise resp. they will worsen EMC.

In other words: a long transmission line acts like an antenna, and then higher the resistance between driver and logic inputs, than higher the danger that shift registers will get additional clocks (sporadically) in noisy environments (e.g. if you turn on/off another device)

There are a few points to make:

-Relatively low series resistances slow the edges sufficient to reduce ringing (at least in my case). The circuit has a 220R pullup. I've added 100R in series (maybe smaller will work). It was only the falling edge (open drain) that energised the ringing.

-There are other ways of controlling edge rise/fall time that are not increasing the resistance. e.g parallel capacitance reduces series impedance (for high frequencies), also configuring a driver that has a controlled edge speed does not have to increase series resistance.

Having said this I need to look at how my circuit and the MBHP layouts differ. I have routed my PCB MKLD Double sided with a ground plain to reduce the inductance (potentially increasing the capacitance somewhat, I'll measure this). I suspect that the traditional MBHP layouts have significant inductance. (Minimizing the effective area of the signal/return current path is the main way of minimizing inductance. Inductively coupled noise spikes are thus avoided. )The point here is that my method of slowing the clock edge that worked for MKLD may not work so well for traditional DOUT chains.

I will do some measurements with an LCR meter I have access to. I might even purchase a bunch of DOUT PCB's to test.

The simplified telegrapher's equation for characteristic impedance is sqrt(L/C). It ignores series resistance R and leakage G, a safe assumption for us. I will first of all measure the inductance of the SCLK (shorted to ground at far end) and then capacitance for a length of ribbon, then including the chain of SR's.

I'll look at the effect of the position of GND in the cable. I think the best is to have GND in between DOUT/DIN and SLCK. I'll try to quantify the significance of this. Also comparing this to shielded multicore.

Future revisions

-If we accept the fact that ribbons have a characteristic impedance of 100R, then we can design our layouts to match this. This then allows for 100R (AC or DC) termination which makes for much less EMC susceptibility. i.e impedance matched systems are much more noise immune.

-It may be possible to compile some design rules for user project MBHP PCBs to follow in order to produce controlled impedance designs and importantly when not to bother (such as your "16 shift register chain is fine" guideline).

I'm beginning to think that controlled impedance layouts are the way of the future. The point relating EMC performance with impedance matching is made very clearly in the article I reference in the Blog article.

Who wants to be on stage (or similar critical situation) when lighting equipment creates a spike that brings down one's midibox !!!!

[Marxon]

Hi Duggle,

yeah this is an old topic but:

I'll look at the effect of the position of GND in the cable. I think the best is to have GND in between DOUT/DIN and SLCK. I'll try to quantify the significance of this. Also comparing this to shielded multicore.
 

 

What have your tests revealed?

Does it make sense to put GND between DOUT/DIN and SLCK?

 

 

Best regards

Marxon

[Duggle]

I don't have anything fresh to add right now.

As a general rule: try to minimize the area of the loop formed by the conductor and it's ground return path. That means trying to keep the signal close to the ground from transmission to reception.

[Marxon]

Thanks for your reply Duggle!

But would you please explain it a little bit less technical for me? :flowers:

Thanks again!

[Duggle]

Its simple really. If you consider the track carrying the signal and the ground, a pair of conductors, the current flows in a loop from the signal source, down the wire, into the input of the receiver, then in the ground path back to the supply.

By "keeping close" the signal and the ground return tracks, the inductance property of the circuit is minimized so that the signal integrity is better.

When talking of minimizing the loop area, it is the physical area created considering the path of current.

A quick google yielded this reference: http://books.google.com.au/books?id=qeWWXvuAXXoC&pg=PA161&lpg=PA161&dq=signal+integrity+loop+area&source=bl&ots=DwrZuxjpAA&sig=jPSFMB_2fMMhU3941Nei99cgPU4&hl=en&sa=X&ei=7AHSUtiaH4iPiAf3z4DYCQ&ved=0CEUQ6AEwAQ#v=onepage&q=signal%20integrity%20loop%20area&f=false

 

 

[FantomXR]

I know this is an old thread. But my question fits into this topic I think.

What is the "professional" way to place the shift registers? Is it better to place them near the MCU to keep SPI-traces as short as possible or is it better to place them near the objects, that are connected to it (resp. buttons or LEDs)? 

I already designed tons of PCBs and I used to put the SRs near the objects which are connected to the SRs. But meanwhile I don't see really much sense in it. It means a lot routing and starting from scratch with any new PCB. 

How do you do it?

[latigid on]

Is there a specific problem you are trying to solve? 

My gut feeling is that we should minimise the length of high-speed digital signals (lower impedance/inductance causing signal-integrity loss; less EMI) and buffer them to take load off the MCU, also minimising the number of interconnections. Things that interface to the shift registers (LEDs, switches) are much slower and could run over longer traces or cables.

In practice I'm not sure if it really matters. Try for logical layouts and see how the performance is.

[FantomXR]

6 minutes ago, latigid on said:

Is there a specific problem you are trying to solve? 

I guess that routing is way more comfortable and even better if I place all SRs on one PCB next to each other and use pinheader to connect the buttons & LEDs to it directly. For some I reason I never did it like this... 

I never had performance problems anyway... so I'm just interested how it is done in the professional world...

[Duggle]

The usual way is to have the shift registers close to where their io is needed. This minimises interconnects and tracks. The high speed serial wires can be kept reliable and quiet with source impedance matching resistor on the clock line IIRC.