jjonas

The FPGASID Project

12 posts in this topic

I really appreciate the efforts of the FPGA SID devs. I think that providing a critical components in keeping the legacy boxes running is commendable (even though the VIC II and PLA are still looming issues).....however....I have a psychological bug that will just not allow me to forget it is not a real SID...no matter how insignificant the differences may be.

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12 hours ago, ChinMuzik said:

I have a psychological bug that will just not allow me to forget it is not a real SID...no matter how insignificant the differences may be.

Just have someone build the unit for you, then you don't know what is inside :grin:.

Seriously, the production spread on the original chips (6581) was so large that your FPGA version might exactly replicate one of those.

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I don't think I'd build a new MIDIbox specifically to put these in, but I'll happily grab a full set to have when real replacement SIDs finally become impossible to find.

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It is a very interesting development for sure, especially, if they managed to keep the chip noise levels down :-). I guess it all depends on how close to the original the FPGA emulation is...

Many greets,
Peter

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The digital section is supposed to be cycle-for-cycle accurate once all is said and done. The analog emulation will be tougher, but the sound demos are very encouraging.

The plus side is that you could theoretically "fix" any of your least favorite SID issues. Want to use the volume envelope without the infamous bug? No problem. Want to boost the resonance a bit to get a really nice acid bassline? Do it.

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I'm in contact with the designer.

The good news: he plans a public release of all sources, which means that it will be possible to change the HW interface so that it can be directly connected to the core w/o need for serial shift registers! :happy:

It might even be possible to use a bigger FPGA for the emulation of 8 SIDs, all connected to a single SPI which will be the best way how to control the SIDs from a MBHP_CORE_STM32F4 module.

Best Regards, Thorsten.

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4 hours ago, TK. said:

I'm in contact with the designer.

The good news: he plans a public release of all sources, which means that it will be possible to change the HW interface so that it can be directly connected to the core w/o need for serial shift registers! :happy:

It might even be possible to use a bigger FPGA for the emulation of 8 SIDs, all connected to a single SPI which will be the best way how to control the SIDs from a MBHP_CORE_STM32F4 module.

Best Regards, Thorsten.

...holy shit!

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Update: I got one of the last 2 prototypes from Andi so that I can test the device before the next batch run. :)

mb6582_fpgasid.jpg

Target is to test all functions, and to prepare direct shift register based access, so that the module could be directly connected to a MIOS8 or MIOS32 core w/o MBHP_SID module :)

The sound is *very* close to the original.
I will provide a A/B comparison soon.

Best Regards, Thorsten.

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This is so sweet! I'd love build my next MBSID based on eight psuedovirtual SID chips in an FPGA. I'd keep my MB6582 for reference of course, but a noiseless and potentially bug free version would know its place from time to time.

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It would be cool if they could shrink it down to SID size, those are machine stuffed anyway so no reason not to go to a TAG programming header, 0402 passive, small as possible everything else (underneath?)

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On 11/28/2016 at 11:26 PM, TK. said:

It might even be possible to use a bigger FPGA for the emulation of 8 SIDs, all connected to a single SPI which will be the best way how to control the SIDs from a MBHP_CORE_STM32F4 module.

 

Even a board for multiple FPGA chips would be cool

I wonder if they sound so close I would fail in a blind test and also if they are capable to do the pseudo-sampling thing, would be really sweet given the power of STM32F4

A MIOS32 port of MBSID could also enable sampling features even on real SID chips!

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