Hi Rosch,
Pin 4 of J2 would be Dout, e.g. for chaining multiple AOUTs to one core, I think you mean Pin 4 of J1? Anyways, the Wiki says that even chaining is not supported by any existing apps.
If I understand things correctly the TLV runs SPI. SPI is not a multi-master bus, so there's no collision handling if several cores would like to write data to it at the same time. Had this been doing I2C that would have been fixable, but the SID portion of the app also doesn't share envelope, LFOs or such data globally across themselves. Therefore each core only knows what it is doing, not the status of others unless MB-NET got extended. All this is AFAIK, TK or other gurus could say otherwise.
Also, this has been stated before in the forums But, on a positive note: You could share the quad VCA board across since each VCA has its own CVs, just connect those where applicable. However, the full-on 4-pair stereo SSM filtering requires 4x dual SSM2044 PCBs, along with 8 SSM 2044ICs and all the rest.
It could end up being costly, but given the lengths people will go to pimping their SID synths, why not?
Cheers,
J